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CS82C55A-5 View Datasheet(PDF) - Harris Semiconductor

Part NameCS82C55A-5 Harris
Harris Semiconductor Harris
DescriptionCMOS Programmable Peripheral Interface
CS82C55A-5 Datasheet PDF : 26 Pages
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82C55A
INTERRUPT
REQUEST
PC3 PA0
PA1
PA2
PA3
PA4
PA5
MODE 1
(INPUT)
PA6
PA7
PC4
PC5
R0
R1
R2
R3
FULLY
DECODED
R4 KEYBOARD
R5
SHIFT
CONTROL
STROBE
ACK
82C55A
PB0
PB1
PB2
PB3
PB4
MODE 1 PB5
(OUTPUT) PB6
PB7
B0
B1
B2 BURROUGHS
B3 SELF-SCAN
B4
DISPLAY
B5
BACKSPACE
CLEAR
PC1
DATA READY
PC2
ACK
PC6
BLANKING
PC7
CANCEL WORD
INTERRUPT
REQUEST
FIGURE 19. KEYBOARD AND DISPLAY INTERFACE
INTERRUPT
REQUEST
PC3 PA0
PA1
PA2
PA3
PA4
PA5
MODE 1
(INPUT)
PA6
PA7
PC4
82C55A PC5
PC6
PC7
PB0
PB1
PB2
MODE 0 PB3
(INPUT) PB4
PB5
PB6
PB7
R0
R1
R2
R3
FULLY
DECODED
R4 KEYBOARD
R5
SHIFT
CONTROL
STROBE
ACK
BUST LT
TEST LT
TERMINAL
ADDRESS
FIGURE 20. KEYBOARD AND TERMINAL ADDRESS
INTERFACE
PA0
PA1
PA2
PA3
PA4
MODE 0 PA5
(OUTPUT) PA6
PA7
PC4
PC5
PC6
PC7
82C55A
PC0
PC1
BIT
SET/RESET PC2
PC3
PB0
PB1
PB2
MODE 0 PB3
(INPUT) PC4
PC5
PC6
PC7
LSB
12-BIT
A/D
CONVERTER
(DAC)
STB DATA
SAMPLE EN
STB
LSB
8-BIT
D/A
CONVERTER
(ADC)
MAB
ANALOG
OUTPUT
ANALOG
INPUT
FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL
INTERRUPT
REQUEST
PC3 PA0
PA1
PA2
PA3
PA4
PA5
MODE 1
(OUTPUT)
PA6
PA7
PC7
PC6
PC5
PC4
82C55A
PC2
PC1
PC0
PB0
MODE 0 PB1
(OUTPUT) PB2
PB3
PB4
PB5
PB6
PB7
R0
R1
R2
CRT CONTROLLER
R3
CHARACTER GEN.
R4
REFRESH BUFFER
R5
CURSOR CONTROL
SHIFT
CONTROL
DATA READY
ACK
BLANKED
BLACK/WHITE
ROW STB
COLUMN STB
CURSOR H/V STB
CURSOR/ROW/COLUMN
ADDRESS
H&V
FIGURE 22. BASIC CRT CONTROLLER INTERFACE
15
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Description
The Harris 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors.
Static CMOS circuit design insures low operating power. TTL compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. The Harris advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power.

Features
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and
   8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA

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