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Y59208F View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
Y59208F 8-BIT FM+ I2C BUS LED DRIVER TI
Texas Instruments TI
Y59208F Datasheet PDF : 27 Pages
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TLC59208F
SCLS715 – MARCH 2009 .................................................................................................................................................................................................. www.ti.com
I2C INTERFACE TIMING REQUIREMENTS
TA = –40°C to 85°C
I2C Interface
STANDARD-MODE
I2C BUS
MIN
MAX
FAST-MODE
I2C BUS
MIN
MAX
FAST-MODE PLUS
I2C BUS
UNIT
MIN
MAX
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
tHIGH
tf
SCL clock frequency
I2C bus free time between stop and
start
Hold time (repeated) Start condition
Set-up time for a repeated Start
condition
Set-up time for Stop condition
Data hold time
Data valid acknowledge time(1)
Data valid time(2)
Data set-up time
Low period of the SCL clock
High period of the SCL clock
Fall time of both SDA and SCL
signals (3) (4)
0
100
0
4.7
1.3
4
0.6
4.7
0.6
4
0.6
0
0
0.3
3.45
0.1
0.3
3.45
0.1
250
100
4.7
1.3
4
0.6
300 20+0.1Cb(5)
400
0
1000 kHz
0.5
µs
0.26
µs
0.26
µs
0.26
µs
0
ns
0.9
0.05
0.45 µs
0.9
0.05
0.45 µs
50
ns
0.5
µs
0.26
µs
300
120 ns
tr
Rise time of both SDA and SCL
signals
1000 20+0.1Cb(5)
300
120 ns
tSP
Pulse width of spikes that must be
suppressed by the input filter(6)
50
50
50 ns
Reset
tW
tREC
tRESET
Reset pulse width
Reset recovery time
Time to reset(7)(8)
10
10
10
ns
0
0
0
ns
400
400
400
ns
(1) tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low.
(2) tVD;DAT = minimum time for SDA data out to be valid following SCL low.
(3) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of SCLs falling edge.
(4) The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified
at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
(5) Cb = total capacitance of one bus line in pF.
(6) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns
(7) Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.
(8) Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.
6
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