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Y3574 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
Y3574 5-V ANALOG, 3-/5-V DIGITAL, 14-/12-BIT, 200-KSPS, 4-/8-CHANNEL SERIAL ANALOG-TO-DIGITAL CONVERTERS WIRH ±10-V INPUTS TI
Texas Instruments TI
Y3574 Datasheet PDF : 51 Pages
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TLC3574, TLC3578, TLC2574, TLC2578
5ĆV ANALOG, 3Ć/5ĆV DIGITAL, 14Ć/12ĆBIT, 200ĆKSPS, 4Ć/8ĆCHANNEL
SERIAL ANALOGĆTOĆDIGITAL CONVERTERS WITH ±10ĆV INPUTS
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
circuit description
converter
The converters include a successive-approximation ADC utilizing a charge redistribution DAC. Figure 5 shows
a simplified block diagram of the ADC. The sampling capacitor acquires the signal on Ain during the sampling
period. When the conversion process starts, the control logic directs the charge redistribution DAC to add and
subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition.
When balanced, the conversion is complete and the ADC output code is generated.
Charge
Redistribution
DAC
Ain
_
C(sample)
+
Control
Logic
ADC Code
REFM
Figure 5. Simplified Block Diagram of the Successive-Approximation System
analog input range and internal test voltages
TLC3578 and TLC2578 have 8 analog inputs (TLC3574 and TLC2574 have 4) and three test voltages. The
inputs are selected by the analog multiplexer according to the command entered (see Table 1). The input
multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel
switching.
All converters are specified for bipolar input range of ±10 V. The input signal is scaled to 0–4 V at the SAR ADC
input via the bipolar scaling circuit (see the functional block diagram and the equivalent analog input circuit):
–10 V to 0 V, 10 V to 4 V, and 0 V to 2 V.
analog input mode
Two input signal modes can be selected: single-ended input and pseudodifferential input.
Charge
Redistribution
DAC
S1
Ain(+)
Ain(−)
_
Control
+
Logic
ADC Code
REFM
When sampling, S1 is closed and S2 connects to Ain(−).
During conversion, S1 is open and S2 connects to REFM.
Figure 6. Simplified Pseudodifferential Input Circuit
Pseudodifferential input refers to the negative input, Ain(−). Its voltage is limited in magnitude to ±1 V. The input
frequency limit of Ain(−) is the same as the positive input Ain(+). This mode is normally used for ground noise
rejection or dc offset.
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