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Y3574 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
Y3574 5-V ANALOG, 3-/5-V DIGITAL, 14-/12-BIT, 200-KSPS, 4-/8-CHANNEL SERIAL ANALOG-TO-DIGITAL CONVERTERS WIRH ±10-V INPUTS TI
Texas Instruments TI
Y3574 Datasheet PDF : 51 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
TLC3574, TLC3578, TLC2574, TLC2578
5ĆV ANALOG, 3Ć/5ĆV DIGITAL, 14Ć/12ĆBIT, 200ĆKSPS, 4Ć/8ĆCHANNEL
SERIAL ANALOGĆTOĆDIGITAL CONVERTERS WITH ±10ĆV INPUTS
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted)
SCLK, SDI, SDO, EOC and INT
tc(1)
tw(1)
tr(1)
tf(1)
tsu(1)
th(1)
td(1)
th(2)
td(2)
PARAMETERS
Cycle time of SCLK, 25 pF load (see Note 10)
Pulse width of SCLK High, at 25-pF load
DVDD = 2.7 V
DVDD = 5 V
Rise time for INT and EOC, at 10-pF load
DVDD = 5 V
DVDD = 2.7 V
Fall time for INT and EOC, at 10-pF load
DVDD = 5 V
DVDD = 2.7 V
Setup time, new SDI valid (reaches 90% final level) before the falling edge of SCLK, at 25-pF load
Hold time, old SDI hold (reaches 10% of old data level) after falling edge of SCLK, at 25-pF load
Delay time, new SDO valid (reaches 90% of final level) after SCLK rising edge, at 10-pF
load (see Note 11)
DVDD = 5 V
DVDD = 2.7 V
Hold time, old SDO hold (reaches 10% of old data level) after SCLK rising edge, at 10-pF load
Delay time, delay from the falling edge of 16th SCLK to EOC falling edge, normal sampling, at 10-pF load
MIN TYP
100
40
40%
6
0
0
0
0
0
MAX UNIT
60%
6
10
6
10
10
23
6
ns
tc(1)
ns
ns
ns
ns
ns
ns
ns
td(3) Delay time, delay from the falling edge of 16th SCLK to INT falling edge, at 10-pF load (see Notes 11 and 12) t(conv)
t(conv)+6
ns
NOTES: 9. The minimum pulse width of SCLK high and low is 12.5 ns.
10. Specified by design
11. For normal short sampling, td(3) is the delay from the falling edge of 16th SCLK to the falling edge of INT.
For normal long sampling, td(3) is the delay from the falling edge of 48th SCLK to the falling edge of INT. Conversion time, t(conv),
is equal to 18 × OSC +15 ns (for TLC3574 and TLC3578) or 13 × OSC + 15 ns (for TLC2574 and TLC2578) when using internal
OSC as conversion clock, or 72 × tc(1) + 15 ns (for TLC3574 and TLC3578) or 52 × tc(1) + 15 ns (for TLC2574 and TLC2578) when
external SCLK is conversion clock source.
CS
SCLK
90%
50%
10%
tw(1)
1
tc(1)
16
VIH
VIL
tsu(1)
th(1)
SDI
Don’t Care
ID15 ID1 ID0
Don’t Care
td(1)
th(2)
Hi-Z
SDO
OD15 OD1 OD0
Hi-Z
EOC
td(2)
tr(1)
OR
tf(1)
td(3)
INT
tf(1)
tr(1)
For normal long sampling, td(2) is the delay time of EOC low after the falling edge of 48th SCLK.
For normal long sampling, td(3) is the delay time of INT low after the falling edge of 48th SCLK.
− − − − The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS initiatesthe conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 1. Critical Timing for SCLK, SDI, SDO, EOC and INT
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