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ADV611JST View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADV611JST
ADI
Analog Devices ADI
ADV611JST Datasheet PDF : 46 Pages
First Prev 41 42 43 44 45 46
Parameter
tWR_CD_WRC
tWR_CD_PWA
tWR_CD_PWD
tADR_CD_WRS
tADR_CD_WRH
tDATA_CD_WRS
tDATA_CD_WRH
tACK_CD_WRD
tACK_CD_WROH
ADV611/ADV612
Table XXIX. Host (Compressed Data) Write Timing Parameters
Description
WR Signal, Compressed Data Direct Register, Write Cycle Time
WR Signal, Compressed Data Direct Register, Pulsewidth Asserted
WR Signal, Compressed Data Direct Register, Pulsewidth Deasserted
ADR Bus, Compressed Data Direct Register, Write Setup
ADR Bus, Compressed Data Direct Register, Write Hold
DATA Bus, Compressed Data Direct Register, Write Setup
DATA Bus, Compressed Data Direct Register, Write Hold
ACK Signal, Compressed Data Direct Register, Write Delay
ACK Signal, Compressed Data Direct Register, Write Output Hold
Min Max Unit
28
N/A ns
10
N/A ns
10
N/A ns
2
N/A ns
2
N/A ns
2
N/A ns
2
N/A ns
N/A 19
ns
9
N/A ns
(I) WR
(I) ADR, BE, CS
(I) DATA
tADR CD WRS
tWR CD WRC
tWR CD PWA
VALID
tWR CD PWD
tADR CD WRH
VALID
VALID
VALID
(O) ACK
tDATA CD WRS tDATA CD WRH
tACK CD WRD
tACK CD WROH
Figure 35. Host (Compressed Data) Write Transfer Timing
REV. 0
–43–
 

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