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ADV611JST View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADV611JST
ADI
Analog Devices ADI
ADV611JST Datasheet PDF : 46 Pages
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ADV611/ADV612
TEST CONDITIONS
Figure 22 shows test condition voltage reference and device
loading information. These test conditions consider an output
as disabled when the output stops driving and goes from the
measured high or low voltage to a high impedance state. Tests
measure output disable time (tDISABLE) as the time between the
reference input signal crossing +1.5 V and the time that the
output reaches the high impedance state (also +1.5 V). Simi-
larly, these tests conditions consider an output as enabled when
the output leaves the high impedance state and begins driving a
measured high or low voltage. Tests measure output enable time
(tENABLE) as the time between the reference input signal crossing
+1.5 V and the time that the output reaches the measured high
or low voltage.
INPUT & OUTPUT VOLTAGE/TIMING REFERENCES
INPUT VIH
REFERENCE
SIGNAL
VIL
OUTPUT
SIGNAL
VOH
VOL
1.5V
tDISABLED
1.5V
DEVICE LOADING FOR AC MEASUREMENTS
IOL
tENABLED
TO
OUTPUT
PIN
2pF
+1.5V
IOH
Figure 22. Test Condition Voltage Reference and Device Loading
TIMING PARAMETERS
This section contains signal timing information for the ADV611/ADV612. Timing descriptions for the following items appear in this
section:
Clock signal timing
Video data transfer timing (CCIR-656, and Multiplexed Philips formats)
Host data transfer timing (direct register read/write access)
Clock Signal Timing
The diagram in this section shows timing for VCLK input and VCLKO output. All output values assume a maximum pin
loading of 50 pF.
Table XVII. Video Clock Period, Frequency, Drift and Jitter
Video Format
Min VCLK_CYC
Period
CCIR-601 PAL
CCIR-601 NTSC
35.2 ns
35.2 ns
NOTES
1VCLK Period Drift = ± 0.1 (VCLK_CYC/field.
2VCLK edge-to-edge jitter = 1 ns.
Nominal VCLK_CYC
Period (Frequency)
37 ns (27 MHz)
37 ns (27 MHz)
Max VCLK_CYC
Period1, 2
38.9 ns
38.9 ns
Table XVIII. Video Clock Duty Cycle
VCLK Duty Cycle1
NOTE
1VCLK Duty Cycle = tVCLK_HI/(tVCLK_LO) × 100.
Min
(40%)
Nominal
(50%)
Table XIX. Video Clock Timing Parameters
Max
(60%)
Parameter
tVCLK_CYC
tVCLKO_D0
tVCLKO_D1
Description
VCLK Signal, Cycle Time (1/Frequency) at 27 MHz
VCLKO Signal, Delay (when VCLK2 = 0) at 27 MHz
VCLKO Signal, Delay (when VCLK2 = 1) at 27 MHz
Min
Max
(See Video Clock Period Table)
10
29
10
29
Unit
ns
ns
–34–
REV. 0
 

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