ADV611JST View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADV611JST Datasheet PDF : 46 Pages
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ADV611/ADV612
FL0
FL1
D8–D23
ADSP-2185
PF4
PF5
FL2
RD
WR
IRQ2
IRQL1
THE ADSP-2185 INTERNAL CLOCK RATE
DOUBLE THE INPUT CLOCK
*THE INPUT CLOCK RATE = 1/2 OF THE INTERNAL
CLOCK RATE, RANGING FROM 12 TO 21MHz
ADR0
ADR1
D0–D15
D16–D31
A0–A8
D0–D15
RAS
CAS
WE
ADV611/ADV612
BE0–BE1
BE2–BE3
CS
RD
WR
LCODE
HIRQ
VCLK
VDATA [0–7]
A0–A8
DQ1–DQ16
RAS
CAS
OE DRAM
(256K ؋ 16-BIT)
WEL
WEH
TOSHIBA TC514265DJ/DZ/DFT-60
NEC
PD424210ALE-60
NEC
PD42S4210ALE-60
HITACHI HM514265CJ-60
ANY DRAM USED WITH THE ADV611/ADV612
MUST MEET THE MINIMUM SPECIFICATIONS
OUTLINED FOR THE HYPER MODE DRAMS
LISTED
24.576MHz
XTAL
27MHz PAL OR NTSC
XTAL
LLC
SAA7111
Y[0–7]
COMPOSITE VIDEO INPUT
Figure 16. Alternate Stand-Alone Application Design
Using the ADV611/ADV612 In Stand-Alone Applications
Figure 16 shows the ADV611/ADV612 in a noncomputer
based applications. Here, an ADSP-2185 digital signal proces-
sor provides Host control and BW calculation services. Note
that all control and BW operations occur over the host interface
in this design.
Connecting the ADV611/ADV612 to Popular Video Decoders
and Encoders
The following circuits are recommendations only. Analog
Devices has not actually built or tested these circuits.
Using the Philips SAA7111 Video Decoder
The SAA7111 example circuit, which appears in Figure 17, is
used in this configuration on the ADV611 CCTVPIPE demon-
stration board.
XTAL
XTAL
LLC
SAA7111
Y(0:7)
VCLK
ADV611/ADV612
VDATA (0:7)
(CCIR-656 MODE)
Figure 17. ADV611/ADV612 and SAA7111 Example
Interfacing Block Diagram
Using the Analog Devices ADV7175 Video Encoder
Because the ADV7175 has a CCIR-656 interface, it connects
directly with the ADV611/ADV612 without “glue” logic. Note
that the ADV7175 can only be used at CCIR-601 sampling
rates.
The ADV7175 example circuit, which appears in Figure 18, is
used in this configuration on the ADV611 CCTVPIPE demon-
stration board.
ADV7175
BLANK
CLOCK
P7–P0
ALSB
(MODE 0 & SLAVE MODE)
10k⍀
150⍀
XTAL
XTAL VCLK
VCLKO
VDATA (7:0)
ADV611/ADV612
(CCIR-656 MODE)
Figure 18. ADV611/ADV612 and ADV7175 Example
Interfacing Block Diagram
Using the Raytheon TMC22153 Video Decoder
Raytheon has a whole family of video parts. Any member of the
family can be used. The user must select the part needed based
on the requirements of the application. Because the Raytheon
part does not include the A/Ds, an external A/D is necessary in
this design (or a pair of A/Ds for S video).
The part can be used in CCIR-656 (D1) mode for a zero con-
trol signal interface. Special attention must be paid to the video
output modes in order to get the right data to the right pins (see
the following diagram).
Note that the circuit in Figure 19 has not been built or tested.
XTAL CLOCK
TMC22153
Y(2:9)
VCLK
VCLK
ADV611/ADV612
VDATA (0:7)
MODE SET TO:
CDEC = 1
YUVT = 1
F422 = X
(CCIR-656 & SLAVE MODE)
Figure 19. ADV611/ADV612 and TMC22153 Example
CCIR-656 Mode Interface
REV. 0
–31–
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