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P80C31BH-2 View Datasheet(PDF) - Intel

Part Name
Description
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P80C31BH-2 Datasheet PDF : 21 Pages
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87C51 80C51BH 80C31BH
PROGRAMMING THE 87C51
The part must be running with a 4 MHz to 6 MHz
oscillator The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is ap-
plied to data lines Control and program signals must
be held at the levels indicated in Table 4 Normally
EA VPP is held at logic high until just before
ALE PROG is to be pulsed The EA VPP is raised to
VPP ALE PROG is pulsed low and then EA VPP is
returned to a high (also refer to timing diagrams)
DEFINITION OF TERMS
ADDRESS LINES P1 0 – P1 7 P2 0 – P2 5 P3 4 re-
spectively for A0 – A14
DATA LINES P0 0 – P0 7 for D0 – D7
CONTROL SIGNALS RST PSEN P2 6 P2 7 P3 3
P3 6 P3 7
PROGRAM SIGNALS ALE PROG EA VPP
NOTE
 Exceeding the VPP maximum for any amount of
time could damage the device permanently The
VPP source must be well regulated and free of
glitches
Table 4 EPROM Programming Modes
Mode
Program Code Data
RST
H
PSEN
L
ALE
PROG
EA
VPP
12 75V
P2 6
L
Verify Code Data
H
L
H
H
L
Program Encryption
Array Address 0–3F
H
L
12 75V L
Program Lock Bits Bit 1 H
L
12 75V H
Bit 2 H
L
12 75V H
Bit 3 H
L
12 75V H
Read Signature Byte
H
L
H
H
L
P2 7
H
L
H
H
H
L
L
P3 3
H
L
H
H
H
H
L
P3 6
H
H
L
H
L
H
L
P3 7
H
H
H
H
L
L
L
See Table 4 for proper input on these pins
Figure 10 Programming the EPROM
272335 – 21
17
 

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