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TEA1098AH View Datasheet(PDF) - Philips Electronics

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TEA1098AH
Philips
Philips Electronics Philips
TEA1098AH Datasheet PDF : 40 Pages
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Philips Semiconductors
Speech and handsfree IC
Preliminary specification
TEA1098A
Transmit channels (pins MIC+, MIC, DTMF, HFTX
and LN)
HANDSET MICROPHONE AMPLIFIER (PINS MIC+, MIC
AND LN)
The TEA1098A has symmetrical microphone inputs. The
input impedance between pins MIC+ and MICis typically
70 k. The voltage gain between pins MIC+/MICand LN
is set to 44.3 dB. Without limitation from the output, the
microphone input stage can accommodate signals up to
18 mV (RMS) at room temperature for 2% of Total
Harmonic Distortion (THD). The microphone inputs are
biased at one diode voltage.
Automatic gain control is provided for line loss
compensation.
DTMF AMPLIFIER (PINS DTMF, LN AND RECO)
The TEA1098A has an asymmetrical DTMF input. The
input impedance between pins DTMF and GND is typically
20 k. The voltage gain between pins DTMF and LN is set
to 25.35 dB. Without limitation from the output, the input
stage can accommodate signals up to 180 mV (RMS) at
room temperature for 2% of THD.
When the DTMF amplifier is enabled, dialling tones may
be sent on the line. These tones can be heard in the
earpiece or in the loudspeaker at a low level. This is called
the confidence tone. The voltage attenuation between pins
DTMF and RECO is typically 16.5 dB in handsfree mode
(HFC HIGH), and 28.2 dB in handset mode (HFC LOW).
The DC biasing of this input is 0 V.
The automatic gain control has no effect on these
channels.
HANDSFREE TRANSMIT AMPLIFIER (PINS HFTX AND LN)
The TEA1098A has an asymmetrical HFTX input, which is
mainly intended for use in combination with the TXO
output. The input impedance between pins HFTX and
GND is typically 20 k. The voltage gain between pins
HFTX and LN is set to 34.7 dB. Without limitation from the
output, the input stage can accommodate signals up to
95 mV (RMS) at room temperature for 2% of THD. The
HFTX input is biased at two diodes voltage.
Automatic gain control is provided for line loss
compensation.
Receive channels (pins IR, RECO, GARX, EARO
and EVCI)
RX AMPLIFIER (PINS IR, RECO AND EVCI)
The receive amplifier has one input IR which is referred to
the line. The input impedance between pins IR and LN is
typically 20 kand the DC biasing between these pins is
equal to one diode voltage.
When HFC = 0, the gain between pins IR (referred to LN)
and RECO is typically 17.0 dB which compensates
typically 15 dB lower than attenuation of the anti-sidetone
network. The receive amplifier gain can be digitally
increased with the 4-level logic input EVCI, providing
4 steps of 4.85 dB which apply in all handset receive
modes. Without limitation from the output, the input stage
can accommodate signals up to 50 mV (RMS) at room
temperature for 2% of THD.
When HFC = 1, the gain is set automatically to 29.7 dB
which compensate the anti-sidetone network attenuation
minus 2.3 dB.
This receive amplifier has a rail-to-rail output RECO, which
is designed for use with high ohmic (real) loads (larger
than 5 k). This output is biased at two diodes voltage.
Automatic gain control is provided for line loss
compensation.
EARPIECE AMPLIFIER (PINS GARX AND EARO)
The earpiece amplifier is an operational amplifier having
its output (EARO) and its inverting input (GARX) available.
Its input signal comes, via a decoupling capacitor, from the
receive output RECO. It is used in combination with two
resistors to get the required gain or attenuation compared
to the receive gain. The typical resistor ratio is 4, which
gives a 12 dB gain. The gain range can be chosen
between 0 dB and 20 dB.
Two external capacitors CGAR (connected between pins
GAR and EARO) and CGARS (connected between pins
GAR and GND) ensure stability. The CGAR capacitor
provides a first-order low-pass filter. The cut-off frequency
corresponds to the time constant CGAR × RE2. The
relationship CGARS > = 10 × CGAR must be fulfilled.
The earpiece amplifier has a rail-to-rail output EARO,
biased at two diodes voltage. It is designed for use with low
ohmic (real) loads (150 ) or capacitive loads (100 nF in
series with 100 ).
2000 Mar 21
11
 

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