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TEA1065 View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
TEA1065 Versatile telephone transmission circuit with dialler interface Philips
Philips Electronics Philips
TEA1065 Datasheet PDF : 28 Pages
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Philips Semiconductors
Versatile telephone transmission circuit with
dialler interface
Product specification
Power-down input PD
During pulse dialling or register recall (timed-loop-break)
the telephone line is interrupted, consequently it provides
no supply for the transmission circuit and the peripherals
connected to VCC. These gaps have to be bridged by the
charge in the smoothing capacitor C1. The requirement on
this capacitor is relaxed by applying a HIGH level to the PD
input during the loop-break. This reduces the internal
supply current from typ. 1.14 mA to 73 µA.
A HIGH level at PD also disconnects the capacitor at REG
which results in the voltage stabilizer having no switch-on
delay after line interruptions. This results in no contribution
of the IC to the current waveform during pulse dialling or
register recall. When this facility is not required PD may be
left open-circuit or connected to VEE. An electrostatic
discharge protection diode is connected between pin PD
and VCC.
Digital pulse input DPI
A HIGH level at DPI creates a current which flows from pin
DOC to VEE in order to interrupt the line current by the
external line current control transistor (see Fig.18;
MOSFET BUK554). A LOW level (or pin left open-circuit)
disables this current to provide the normal DC regulation
(voltage or current). A simple application without
regulation of current in pulse dialling mode is given in
When DPI is activated (HIGH level), the external line
current control transistor is switched off resulting in no
current in the TEA1065. The voltage on pin SLPE
becomes zero and capacitor C15 discharges cancelling
the current regulation when DPI becomes inactive (LOW
To provide a constant regulation (in speech mode and
pulse mode), an external transistor is required to keep C15
charged during DPI active (see Fig.19 in which the Field
Effect Transistor BSJ177 is directly driven by the DPI
An electrostatic discharge protection diode is connected
between pin DPI and pin VCC.
Voltage sense input and reference voltage input VSI
and REFI
The voltage on pin VSI represents the DC voltage of pin
SLPE. The RC filter (R15 × C15) is also intended to
disable the DC regulation when C15 is shunted or not yet
charged (especially directly after hook-off). The time
constant R15 × C15 determines approximately the time
when no regulation (except CURL pin limitation) is
The voltage applied on pin REFI represents a fraction of
the bandgap reference voltage given by pin VBG (resistor
tap R13 and R14) in order to determine Iknee.
Drive current output DOC
Pin DOC drives the external line current control transistor
in order to achieve line interruption during pulse dialling (or
register recall) and also the DC slope when Iline > Iknee.
The current sunk by pin DOC is determined by the voltage
on pin VSI in comparison with the voltage on pin VBG
divided by the resistor tap R13 and R14.
When pin DPI is activated, pin DOC changes to a low
voltage (by trying to sink typ. 900 µA to VEE) to switch off
the external line current control transistor.
Bandgap reference output VBG
This output provides a voltage reference to set the knee
line current with the following formula:
Iknee = ICC + IP +
(VBG/R9) × {R14/(R14 + R13)} (R15/R9) × 2.5 × 106
In order to improve stability, a capacitive load is not
allowed on this output.
Current limit input CURL
This input is applied to the base of an internal NPN
transistor which has its collector connected to pin DOC
and its emitter to VEE (see Fig.13). The transistor limits the
line current just after hook-off or during line transients to a
value given by the following formula:
Ihook-off = I(R1) + VBE/R9b
VBE is the base-emitter voltage of the transistor
(typ. 700 mV at 25 °C). I(R1) is the current flowing through
R1 to charge C1 just after hook-off.
handbook, halfpage
IC (collector current)
Fig.13 Internal current limiting transistor.
March 1994
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