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28F004S5 SMART 5 FlashFile™ MEMORY FAMILY 4, 8, AND 16 MBIT Intel
Intel Intel
28F004S5 Datasheet PDF : 37 Pages
First Prev 31 32 33 34 35 36 37
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
6.2.6
COMMERCIAL TEMPERATURE AC CHARACTERISTICS - WRITE OPERATIONS(1,2)
Commercial Temperature Write Operations for
4-, 8-, and 16-Mbit Smart 5 FlashFile™ Memories at TA = 0°C to +70°C
Versions(4)
5V ± 5%, Valid for All
5V ± 10% VCC Speeds Unit
#
Sym
Parameter
Notes Min Max
W1 tPHWL (tPHEL) RP# High Recovery to WE# (CE#) Going Low
3
1
µs
W2 tELWL (tWLEL) CE# (WE#) Setup to WE# (CE#) Going Low
7
0
ns
W3 tWP
Write Pulse Width
7 50
ns
W4 tDVWH (tDVEH) Data Setup to WE# (CE#) Going High
4 40
ns
W5 tAVWH (tAVEH) Address Setup to WE# (CE#) Going High
4 40
ns
W6 tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High
0
ns
W7 tWHDX (tEHDX) Data Hold from WE# (CE#) High
5
ns
W8 tWHAX (tEHAX) Address Hold from WE# (CE#) High
5
ns
W9 tWPH
Write Pulse Width High
8 25
ns
W10 tPHHWH (tPHHEH) RP# VHH Setup to WE# (CE#) Going High
3 100
ns
W11 tVPWH (tVPEH) VPP Setup to WE# (CE#) Going High
3 100
ns
W12 tWHGL (tEHGL) Write Recovery before Read
0
ns
W13 tWHRL (tEHRL) WE# (CE#) High to RY/BY# Going Low
90 ns
W14 tQVPH
RP# VHH Hold from Valid SRD, RY/BY# High
3,5 0
ns
W15 tQVVL
VPP Hold from Valid SRD, RY/BY# High
3,5 0
ns
NOTES:
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Refer to Table 3 for valid AIN and DIN for block erase, program, or lock-bit configuration.
5. VPP should be held at VPPH1/2 (and if necessary RP# should be held at VHH) until determination of block erase, program, or
lock-bit configuration success (SR.1/3/4/5 = 0).
6. See Ordering Information for device speeds (valid operational combinations).
7. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CE# is driven low 10 ns before WE# going low,
WE# pulse width requirement decreases to tWP - 20 ns.
8. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
32
PRODUCT PREVIEW
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