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28F004S5 Ver la hoja de datos (PDF) - Intel

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28F004S5 SMART 5 FlashFile™ MEMORY FAMILY 4, 8, AND 16 MBIT Intel
Intel Intel
28F004S5 Datasheet PDF : 37 Pages
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E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
6.2.2
AC INPUT/OUTPUT TEST CONDITIONS
3.0
INPUT
1.5
TEST POINTS
1.5 OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 12. Transient Input/Output Reference Waveform for VCC = 5.0V ± 5%
(High Speed Testing Configuration)
2.4
2.0
INPUT
TEST POINTS
2.0
OUTPUT
0.8
0.8
0.45
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for VCC = 5.0V ± 10%
(Standard Testing Configuration)
DEVICE
UNDER
TEST
1.3V
1N914
RL = 3.3 K
OUT
CL
Test Configuration Capacitance Loading Value
Test Configuration
CL (pF)
VCC = 5.0V ± 5%
30
VCC = 5.0V ± 10%
100
NOTE:
CL includes Jig Capacitance
Figure 14. Transient Equivalent Testing
Load Circuit
PRODUCT PREVIEW
27
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