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28F004S5 SMART 5 FlashFile™ MEMORY FAMILY 4, 8, AND 16 MBIT Intel
Intel Intel
28F004S5 Datasheet PDF : 37 Pages
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E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Read Status
Register
0
SR.7 =
1
Full Status
Check if Desired
Set Lock-Bit Complete
Bus
Operation
Write
Write
Read
Command
Comments
Set
Block/Master
Lock-Bit Setup
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Set
Block or Master
Lock-Bit Confirm
Data = 01H (Block),
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Status Register Data
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1
SR.3 =
0
1
SR.1 =
0
1
SR.4,5 =
0
1
SR.4 =
0
VPP Range Error
Device Protect Error
Command Sequence
Error
Set Lock-Bit Error
Set Lock-Bit Successful
Bus
Operation
Command
Comments
Standby
Standby
Standby
Standby
Check SR.3
1 = VPP Error Detect
Check SR.1
1 = Device Protect Detect
RP# = VIH,
(Set Master Lock-Bit Operation)
RP# = VHH, Master Lock-Bit Is Set
(Set Block Lock-Bit Operation)
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.4
1 = Set Lock-Bit Reset Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set before
full status is checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Figure 10. Set Block and Master Lock-Bit Flowchart
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