TDA8012A View Datasheet(PDF) - Philips Electronics
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Description
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TDA8012A Datasheet PDF : 16 Pages
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Philips Semiconductors
Low power PLL FM demodulator for
satellite TV receivers
Product specification
TDA8012AM
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Automatic gain control (note 12)
THAGC
automatic gain control threshold as a
function of the voltage applied to pin 10
note 13
LD
SAGC
Vsat(AGC)
level detector
shift
drift
automatic gain control steepness
low level automatic gain control output
saturation voltage
IAGCO = 0.5 mA;
−
V10 = 0.1VCC
IAGCO = 0.5 mA;
61
V10 = 0.9VCC
Vth(AGC) (pin 10) not
−
connected
VCC = 4.75 to 5.25 V
−
Tamb = −10 to +80 °C
−
IAGCO = 0.5 mA; note 14 −
IAGCO = 1 mA
−
−
53
dBµV
−
−
dBµV
57
−
dBµV
1
−
dB
1
−
dB
8
−
mA/dB
200 500 mV
Keying pulse
tkey
tW(key)
VIL
VIH
Zi
input keyed pulse time period
keyed pulse width
LOW level input keyed pulse voltage
HIGH level input keyed pulse voltage
input impedance
AFC and carrier detector output (note 15)
IL(pd)
∆-----V-∆---A-f--F---C-
peak detector leakage current
automatic frequency control steepness
with unmodulated input signal
key on
key off
note 16
−
64
8
−
−
−
3.0
−
1
10
−
µs
−
µs
0.8
V
−
V
−
kΩ
50
150 250 nA
4.5
5.5
6.5
V/MHz
∆fAFC(shift)
shift of automatic frequency control
voltage with respect to fVCO with
unmodulated 480 MHz input signal
∆VCC = ±5%
−
±180 ±500 kHz
∆fAFC(drift) drift of automatic frequency control
voltage with respect to fVCO
Tamb = 80 °C; note 17 −
−1.1 −
MHz
Notes
1. The DC supply current is measured with VCC = 5 V.
2. The VCO frequency drift is defined as the change in oscillator frequency for a variation of ambient temperature, on
the one hand from Tamb = 25 °C to Tamb = 0 °C and on the other hand from Tamb = 25 °C to Tamb = 50 °C. It is
measured in the application of Fig.4 with the following component values for the tank circuit:
Coil: 2.5 turns; diameter 2 mm; adjustable.
Capacitor: miniature ceramic plate capacitor NP0, 3.3 pF.
3. The circuit is designed for an input level of 57 dBµV. The maximum allowable input level for the PLL design is
61 dBµV. However, for levels different from 57 dBµV, the optimum loop filter values will be different from those given
for the 57 dBµV input level in the reference measuring set-up.
4. The input impedance is reduced to a resistor with a parallel reactance. The values are given at 480 MHz. In order to
reduce the radiation from the oscillator to the RF input, it is recommended to use a symmetrical drive.
5. The PLL loop gain shift and drift are given without loop filter shift and drift (non-temperature compensated external
components).
1997 May 26
7
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