TDA8005AG View Datasheet(PDF) - Philips Electronics
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TDA8005AG Datasheet PDF : 36 Pages
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Philips Semiconductors
Low-power (3 V/5 V) smart card coupler
Preliminary specification
TDA8005A
FUNCTIONAL DESCRIPTION
Microcontroller
The microcontroller is a P80CL51 with 256 bytes of RAM
instead of 128. The baud rate of the UART has been
multiplied by four in modes 1, 2 and 3. This means that the
division factor of 32 in the formula is replaced by 8 in both
reception and transmission mode and that in the reception
modes only four samples per bit are taken with decision on
the majority of samples 2, 3 and 4; the delay counter has
been reduced from 1536 to 24 as well.
Remark: this has an impact when getting out of
power-down mode. It is recommended to switch to
internal clock before entering power-down mode.
All the other functions remain unchanged. Refer to the
P80CL51 data sheet for any further information. Internal
ports INT0 (P32), P10, P04 to P07 and P24 to P27 are
used for controlling the smart card interface.
Mode 0 is unchanged. The baud rate for modes 1 and 3 is:
2----S---M8----O---D-- × 1----2-----×------(--2---5f--c--6-l-k---–----T----H----1----)-
The baud rate for mode 2 is:
-2---S--1-M--6--O---D-- × fclk
For mode 3 timing see Table 1.
Supply
The circuit operates within a supply voltage range of
2.5 to 6 V. The supply pins are VDDD, VDDA, DGND and
AGND. Pins VDDA and AGND supply the analog drivers to
the card and have to be externally decoupled because of
the large current spikes that the card and the step-up
converter can create. An integrated spike killer ensures
the contacts to the card remain inactive during power-up or
power-down. An internal voltage reference is generated
which is used within the step-up converter, the voltage
supervisor and the VCC generator.
The voltage supervisor generates an internal alarm pulse,
whose length is defined by an external capacitor tied to the
DELAY pin, when VDDD is too low to ensure proper
operation (1 ms per 1 nF typical). This pulse is used as a
reset pulse by the controller, in parallel with an external
reset input, which can be tied to the system controller.
It is also used in order to either block any spurious card
contacts during controllers reset, or to force an automatic
deactivation of the contacts in the event of supply dropout;
see Sections “Activation sequence” and “Deactivation
sequence”.
In the 64 pin version, this reset pulse is output to the open
drain ALARM pin, which may be selected active HIGH or
active LOW by mask option and may be used as a reset
pulse for other devices within the application.
Table 1 Mode 3 timing
BAUD
RATE
135 416
67 708
45 139
33 854
27 083
22 569
16 927
13 542
11 285
fclk = 6.5 MHz;
VDD = 5 V
SMOD TH1
1
255
0
255
1
253
0
254
1
251
0
253
−
−
−
−
0
250
fclk = 3.25 MHz;
VDD = 5 or 3 V
SMOD TH1
−
−
1
255
−
−
0
255
−
−
1
253
0
254
1
251
0
253
1998 Mar 20
9
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