E-TDA7590TR View Datasheet(PDF) - STMicroelectronics
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E-TDA7590TR Datasheet PDF : 40 Pages
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Appendix 1
;;; Bit Definitions for M_TCS
TUFCL
EQU
16
TDE
EQU
15
TUFL
EQU
14
;Reserved
TXIE
EQU
12
TDWE
EQU
11
TREL
EQU
10
TCKP
EQU
9
TLRS
EQU
8
TDIR
EQU
7
TWL1
EQU
6
TWL0
EQU
5
;Reserved
TMME
EQU
3
T2EN
EQU
2
T1EN
EQU
1
T0EN
EQU
0
; Transmitter Data Overflow Clear
; Transmitter Data Ready
; Transmitter Data Overflow
; Transmitter Interrupt Enable
; Transmitter Data Word Justification
; Transmitter Relative Timing
; Transmitter Clock Polarity
; Transmitter Left Right Selection
; Transmitter Data Shift Direction
; Transmitter Word Length Control 1
; Transmitter Word Length Control 0
; Transmitter Master Mode Enable
; Transmitter 2 enable
; Transmitter 1 enable
; Transmitter 0 enable
;------------------------------------------------------------------------
;
EQUATES for CODEC
;------------------------------------------------------------------------
CODEC_CSR EQU
$FFFFCB
; CODEC Control Register Address
;;; Bit Definitions for CODEC
GADCL_0
EQU
0
GADCL_1
EQU
1
GADCL_2
EQU
2
GADCR_0
EQU
3
GADCR_1
EQU
4
GADCR_2
EQU
5
GDACL_0
EQU
6
GDACL_1
EQU
7
GDACL_2
EQU
8
GDACR_0
EQU
9
GDACR_1
EQU
10
GDACR_2
EQU
11
MUTEDAC
EQU
12
PDNDAC
EQU
13
PDNADC
EQU
14
N_RST
EQU
15
; ADC Left Gain Bit 0
; ADC Left Gain Bit 1
; ADC Left Gain Bit 2
; ADC Right Gain Bit 0
; ADC Right Gain Bit 1
; ADC Right Gain Bit 2
; DAC Left Gain Bit 0
; DAC Left Gain Bit 1
; DAC Left Gain Bit 2
; DAC Right Gain Bit 0
; DAC Right Gain Bit 1
; DAC Right Gain Bit 2
; Mute DAC - Active Hi, Reset Val = 1
; Power down DAC - Active Hi, Reset Val = 0
; Power down ADC - Active Hi, Reset Val = 0
; Asynchronoue Reset - Active Lo, Reset Val = 1
;------------------------------------------------------------------------
;
EQUATES for PLL
;------------------------------------------------------------------------
PLL_CSR
EQU
$FFFFD7
; PLL Control/Status Register
PLL_FCR
EQU
$FFFFD6
; PLL Fractional Register
PLL_CLKCTL EQU
$FFFFD5
; PLL Clock Control Register
;;; Bit Definitions for PLL_CSR
IDF0
EQU
0
IDF1
EQU
1
IDF2
EQU
2
IDF3
EQU
3
IDF4
EQU
4
; Reserved
; Input Divide Factor 0
; Input Divide Factor 1
; Input Divide Factor 2
; Input Divide Factor 3
; Input Divide Factor 4
22/40
TDA7590
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