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Q6275K791 View Datasheet(PDF) - Infineon Technologies

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Q6275K791 Datasheet PDF : 186 Pages
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TDA523x
CMC1: Chip Mode Control Register 1
ADDR: 0x03
Bit R/W Description
4 W XTALTREN: XTAL Trim Enable
0: Trimming is disabled
1: Trimming is enabled
Functional Description
Reset Value: 0x00
XTALCAL0: Trim XTAL frequency, coarse
ADDR: 0x61
Reset Value: 0x10
Bit R/W Description
4 W XTAL_SW_COARSE_4: Connect trim capacitor: 16 pF
3 W XTAL_SW_COARSE_3: Connect trim capacitor: 8 pF
2 W XTAL_SW_COARSE_2: Connect trim capacitor: 4 pF
1 W XTAL_SW_COARSE_1: Connect trim capacitor: 2 pF
0 W XTAL_SW_COARSE_0: Connect trim capacitor: 1 pF
XTALCAL1: Trim XTAL frequency, fine
ADDR: 0x62
Reset Value: 0x00
Bit R/W Description
3 W XTAL_SW_FINE_3: Connect trim capacitor: 500 fF
2 W XTAL_SW_FINE_2: Connect trim capacitor: 250 fF
1 W XTAL_SW_FINE_1: Connect trim capacitor: 125 fF
0 W XTAL_SW_FINE_0: Connect trim capacitor: 62.5 fF
2.4.3.2 External Clock Generation Unit
The chip provides a programmable clock signal at the CLKOUT/RXD pin that is derived
from the internal system clock. To save power, this unit can be disabled by the SFR
CLKOUTEN bit. The Clock Generation Unit divides the internal clock by an adjustable
factor down to the desired CLKOUT frequency. The 20-bit wide division factor, stored in
the CLOCKOUT0, CLOCKOUT1 and CLOCKOUT2 registers, allows a CLKOUT-
frequency to be generated down to approximately 10 Hz. The 1:2 divider following the
20-bit counter creates the final CLKOUT signal with 50% duty cycle.
The resulting CLKOUT frequency can be calculated by:
Data Sheet
25
Version 4.0, 2007-06-01
 

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