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TDA1675 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
TDA1675 VERTICAL DEFLECTION CIRCUIT ST-Microelectronics
STMicroelectronics ST-Microelectronics
TDA1675 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
TDA1675A
Figure 6 : PC Board and Components Layout for the Application Circuits of Figures 3, 4 and 5 (1 : 1 scale)
Ro
TDA 1675A
S1
R2
Co
R4
C3
R3
RT1
C11
C4
R9 R1
D1
C6
R5
RT2
R6
C5
C7
R7
C2
C1
R8
C8
R10
C9
R12
GND
R11
SYNC. Iy
IN TEST
YOKE
VS BLANK GND
OUT
APPLICATION INFORMATION (Refer to the
block diagram)
Oscillator and sync gate (Clock generation)
The oscillator is obtained by means of an integrator
driven by a two threshold circuit that switches Ro
high or low so allowing the charge or the discharge
of Co under constant current conditions.
The Sync input pulse at the Sync gate lowers the
level of the upper threshold and than it controls the
period duration. A clock pulse is generated.
Pin 4 is the inverting input of the amplifier used
as integrator.
8/11
Pin 6
Pin 3
Pin 5
is the output of the switch driven by the
internal clock pulse generated by the
threshold circuits.
is the output of the amplifier.
is the input for sync pulses (positive)
Ramp generator and buffer stage
A current mirror, the current intensity of which can
be externally adjusted, charges one capacitor
producing a linear voltage ramp.
The internal clock pulse stops the increasing ramp
by a very fast discharge of the capacitor a new
voltage ramp is immediately allowed.
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