Figure 6 : PC Board and Components Layout for the Application Circuits of Figures 3, 4 and 5 (1 : 1 scale)
VS BLANK GND
APPLICATION INFORMATION (Refer to the
Oscillator and sync gate (Clock generation)
The oscillator is obtained by means of an integrator
driven by a two threshold circuit that switches Ro
high or low so allowing the charge or the discharge
of Co under constant current conditions.
The Sync input pulse at the Sync gate lowers the
level of the upper threshold and than it controls the
period duration. A clock pulse is generated.
Pin 4 is the inverting input of the amplifier used
is the output of the switch driven by the
internal clock pulse generated by the
is the output of the amplifier.
is the input for sync pulses (positive)
Ramp generator and buffer stage
A current mirror, the current intensity of which can
be externally adjusted, charges one capacitor
producing a linear voltage ramp.
The internal clock pulse stops the increasing ramp
by a very fast discharge of the capacitor a new
voltage ramp is immediately allowed.