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TDA1305 View Datasheet(PDF) - Philips Electronics

Part Name
Description
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TDA1305 Datasheet PDF : 20 Pages
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Philips Semiconductors
Stereo 1fs data input up-sampling filter with
bitstream continuous dual DAC (BCC-DAC2)
Preliminary specification
TDA1305T
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Serial input data timing (see Fig.4)
fBCK
bit-clock input (data input fsys = 384fs
rate) frequency
fsys = 256fs
fWS
word select input frequency normal speed
double speed
48fs
MHz
64fs
MHz
25
44.1
48
kHz
50
88.2
96
kHz
tr
tf
tH
tL
tsu
th
tsuWS
thWS
rise time
fall time
bit clock time HIGH
bit clock time LOW
data set-up time
data hold time
word select set-up time
word select hold time
55
55
40
10
40
10
20
ns
20
ns
ns
ns
ns
ns
ns
ns
Notes
1. All VDD and VSS pins must be connected externally to the same supply.
2. Vripple = 1% of supply voltage; fripple = 100 Hz. Ripple rejection RR to VDDA is dependent on the value of the external
capacitor (CEXT3 in Fig.1) connected to Vref. The value here assumes that CEXT3 = 1 µF.
3. Minimum VIL and maximum VIH are peak values to allow for transients.
4. ILImni measured at VI = 0 V; ILImax measured at VI = 5.5 V.
5. Reference levels = 10% and 90%.
ANALOG CHARACTERISTICS
VDD = VDDA = VDDO = 5 V; VSS = 0 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
Reference values
Vref
RCONV
reference voltage level
current-to-voltage
conversion resistor
2.45
1.6
Analog outputs
RES
resolution
VFS(rms)
full-scale output voltage
(pins 23 and 25)
(RMS value)
VOFF
TCFS
output voltage DC offset with
respect to reference voltage
level Vref
full scale temperature
coefficient
1.425
80
TYP.
MAX.
2.5
2.55
2.2
2.8
18
1.5
1.575
65
50
±100 × 106
UNIT
V
k
bit
V
mV
1995 Dec 08
11
 

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