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TC7109 View Datasheet(PDF) - TelCom Semiconductor Inc => Microchip

Part Name
Description
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TC7109
TelCom-Semiconductor
TelCom Semiconductor Inc => Microchip TelCom-Semiconductor
TC7109 Datasheet PDF : 21 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
12-BIT µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
2
3
XTALI
XTAL2
+5V
1 TO
2
4 RESET
21–24,
5 SS
6 INT
P20–P27 35–38 8
8748/8049
CMOS
MICROCOMPUTER
GND 7 EA
8 WR
9 PSEN
11 ALE
+5V 25 PROG
+5V 26 VDD
+5V 39 TL
+5V 40 VCC
P14–P17 31–34 5
P13 30
P12 29
P11 28
P10 27
GND 20 GND
DB0–DB7 12–19
RD 10
+5V 40 V+
REF IN– 39
GND 1 GND
17 TEST
REF CAP– 38
REF CAP+ 37
1µF
EXTERNAL
REFERNCE
OTHER I/O
REF IN+ 36
IN HI 35
34
HI LO
1M
0.01µF
+
+
INPUT
TC7109A
26 RUN/HOLD
33
COM
32
INT
AZ 31
BUFF 30
C INT
CAZ 0.15µF
0.33µF
ANALOG
GND
2 STATUS
REF OUT 29
RINT
18 LBEN
19 HBEN
V – 28 –5V
SEND 27
20k0.2 VREF
10 k1 VREF
BUFF OSC OUT 25
3–8 B9–B12,
6
POL, OR
OSC SEL 24 GND
23
OSC OUT
3.58MHz
8
8
9–16
20
B1–B8
CE/LOAD
22
OSC IN
21
MODE
CRYSTAL
2
3
4
Figure 2. TC7109A Parallel Interface With 8048/8049 Microcomputer
5
DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin DIP)
Analog Section
The functional diagram shows a block diagram of the
analog section of the TC7109A. The circuit will perform
conversions at a rate determined by the clock frequency
(8192 clock periods per cycle), when the RUN/HOLD input
is left open or connected to V+. Each measurement cycle is
divided into four phases, as shown in Figure 3. They are:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference
Deintegrate (DE), and (4) Zero Integrator (ZI).
Auto-Zero Phase
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The reference capacitor is charged to the refer-
ence voltage. A feedback loop is closed around the system
to charge the auto-zero capacitor, CAZ, to compensate for
offset voltage in the buffer amplifier, integrator, and com-
parator. Since the comparator is included in the loop, the AZ
accuracy is limited only by the noise of the system. The offset
referred to the input is less than 10 µV.
TELCOM SEMICONDUCTOR, INC.
Signal-Integrate Phase
The buffer and integrator inputs are removed from
common and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is placed
in series in the loop to provide an equal and opposite
6 compensating offset voltage. The differential voltage be-
tween input high and input low is integrated for a fixed time
of 2048 clock periods. At the end of this phase, the polarity
of the integrated signal is determined. If the input signal has
no return to the converter's power supply, input low can be
tied to analog common to establish the correct common-
mode voltage.
7 Deintegrate Phase
Input high is connected across the previously-charged
reference capacitor and input low is internally connected to
analog common. Circuitry within the chip ensures the ca-
pacitor will be connected with the correct polarity to cause
the integrator output to return to the zero crossing (estab-
lished by auto-zero) with a fixed slope. The time, repre-
sented by the number of clock periods counted for the output
to return to zero, is proportional to the input signal.
8
3-97
 

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