TC7109 View Datasheet(PDF) - TelCom Semiconductor Inc => Microchip
Part Name
Description
View to exact match
TC7109 Datasheet PDF : 21 Pages
| |||
12-BIT µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
1
TC7109
TC7109A
POSITIVE TRANSITION
CAUSES ENTRY INTO
UART MODE
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
MODE INPUT
UART
NORM
INTERNAL MODE
SEND INPUT
CE/LOAD AS OUTPUT
HBEN
HIGH-BYTE DATA
LBEN
LOW-BYTE DATA
STATUS OUTPUT UNCHANGED
IN UART MODE
ZERO CROSSING OCCURS
ZERO CROSSING DETECTED
LATCH PULSE INHIBITED
IN UART MODE
SEND
SENSED
DE PHASE III
SEND
SENSED
SEND
SENSED
TERMINATES
UART MODE
DATA VALID
DATA VALID
2
3
4
= DON'T CARE
=
THREE-STATE
HIGH IMPEDANCE
=
THREE-STATE
WITH PULL-UP
Figure 9. TC7109A Handshake Triggered by MODE Input
5
Oscillator
The oscillator may be overdriven, or may be operated as
an RC or crystal oscillator. The OSCILLATOR SELECT
input optimizes the internal configuration of the oscillator for
RC or crystal operation. The OSCILLATOR SELECT input
is provided with a pull-up resistor. When the OSCILLATOR
SELECT input is HIGH or left open, the oscillator is config-
ured for RC operation. The internal clock will be the same
frequency and phase as the signal at the BUFFERED
OSCILLATOR OUTPUT. Connect the resistor and capaci-
tor as in Figure 10. The circuit will oscillate at a frequency
given by f = 0.45/RC. A 100 kΩ resistor is recommended for
useful ranges of frequency. The capacitor value should be
chosen such that 2048 clock periods are close to an integral
multiple of the 60 Hz period for optimum 60 Hz line rejection.
With OSCILLATOR SELECT input LOW, two on-chip
capacitors and a feedback device are added to the oscillator.
In this configuration, the oscillator will operate with most
crystals in the 1 to 5 MHz range with no external components
(Figure 11). The OSCILLATOR SELECT input LOW inserts
a fixed Ϭ58 divider circuit between the BUFFERED OSCIL-
LATOR OUTPUT and the internal clock. A 3.58 MHz TV
6 crystal gives a division ratio providing an integration time
given by:
t = (2048 clock periods) 58 = 33.18 ms
3.58 MHz
The error is less than 1% from two 60 Hz periods, or
33.33 ms, which will give better than 40 dB, 60 Hz rejection.
The converter will operate reliably at conversion rates up
7 to 30 per second, corresponding to a clock frequency of
245.8 kHz.
When the oscillator is to be overdriven, the OSCILLA-
TOR OUTPUT should be left open, and the overdriving
signal should be applied at the OSCILLATOR INPUT. The
internal clock will be of the same duty cycle, frequency and
phase as the input signal. When the OSCILLATOR SELECT
is at GND, the clock will be 1/58 of the input frequency.
8
TELCOM SEMICONDUCTOR, INC.
3-103
|
|
Share Link: 