T-8207-BAL-DT View Datasheet(PDF) - Agere -> LSI Corporation

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T-8207-BAL-DT

CelXpres™ ATM Interconnect

Agere -> LSI Corporation 

Advance Data Sheet

September 2001

CelXpres T8207

ATM Interconnect

Table of Contents (continued)

Table

Page

Table 1. UTOPIA Pins ........................................................................................................................................... 13

Table 2. Cell Bus Pins ........................................................................................................................................... 14

Table 3. SDRAM Interface Pins ............................................................................................................................ 15

Table 4. Microprocessor Interface Pins ................................................................................................................. 16

Table 5. Translation SRAM Interface ..................................................................................................................... 17

Table 6. JTAG Pins ............................................................................................................................................... 17

Table 7. General-Purpose Pins ............................................................................................................................. 18

Table 8. Power Pins .............................................................................................................................................. 18

Table 9. Loop Filter Register Settings .................................................................................................................... 22

Table 10. Access Times ........................................................................................................................................ 25

Table 11. Active and Ignore Truth Table ............................................................................................................... 31

Table 12. VPI Value Truth Table ........................................................................................................................... 32

Table 13. OAM Routing Control Truth Table ......................................................................................................... 32

Table 14. F5 Translation Record Addresses Table—8-Byte Records ................................................................... 33

Table 15. F5 Translation Record Addresses Table—Extended Mode ................................................................... 40

Table 16. Port Numbering for MPHY Configurations ............................................................................................ 51

Table 17. Supported Memory Configurations ....................................................................................................... 64

Table 18. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 1 ................. 67

Table 19. Queue Organization and Port Group Address/Priority Bits for 32 Ports ................................................ 69

Table 20. Queue Organization and Port Group Address/Priority Bits for 16 Ports with T8207_sel = 0................... 71

Table 21. Instruction Register ............................................................................................................................... 75

Table 22. Boundary-Scan Register Descriptions .................................................................................................. 76

Table 23. Register Map ........................................................................................................................................... 79

Table 24. Identification 0 (IDNT0) (00h) ................................................................................................................ 82

Table 25. Identification 1 (IDNT1) (01h) ................................................................................................................. 82

Table 26. Identification 2 (IDNT2) (02h) ................................................................................................................ 82

Table 27. Direct Configuration/Control Register (DCCR) (28h) ............................................................................. 83

Table 28. Interrupt Service Request (ISREQ) (29h) ............................................................................................. 84

Table 29. mclk PLL Configuration 0 (MPLLCF0) (2Ah) ......................................................................................... 84

Table 30. mclk PLL Configuration 1 (MPLLCF1) (2Bh) ......................................................................................... 85

Table 31. GTL+ Slew Rate Configuration (GTLSRCF) (2Eh) ................................................................................ 85

Table 32. GTL+ Control (GTLCNTRL) (2Fh)........................................................................................................... 85

Table 33. Extended Memory Address 1 (Little Endian) (EMA1_LE) (30h)............................................................. 86

Table 34. Extended Memory Address 2 (Little Endian) (EMA2_LE) (31h)............................................................. 86

Table 35. Extended Memory Address 3 (Little Endian) (EMA3_LE) (32h)............................................................. 86

Table 36. Extended Memory Address 4 (Little Endian) (EMA4_LE) (33h)............................................................. 86

Table 37. Extended Memory Access (Little Endian) (EMA_LE) (34h) ................................................................... 86

Table 38. Extended Memory Data Low (Little Endian) (EMDL_LE) (36h) ............................................................. 87

Table 39. Extended Memory Data High (Little Endian) (EMDH_LE) (37h) ............................................................ 87

Table 40. Extended Memory Address 4 (Big Endian) (EMA4_BE) (30h)............................................................... 88

Table 41. Extended Memory Address 3 (Big Endian) (EMA3_BE) (31h)............................................................... 88

Table 42. Extended Memory Address 2 (Big Endian) (EMA2_BE) (32h)............................................................... 88

Table 43. Extended Memory Address 1 (Big Endian) (EMA1_BE) (33h)............................................................... 88

Table 44. Extended Memory Access (Big Endian) (EMA_BE) (34h) ..................................................................... 89

Table 45. Extended Memory Data High (Big Endian) (EMDH_BE) (36h) .............................................................. 89

Table 46. Extended Memory Data Low (Big Endian) (EMDL_BE) (37h) ............................................................... 89

Table 47. GPIO Output Enable (GPIO_OE) (39h) ................................................................................................. 90

Table 48. GPIO Output Value (GPIO_OV) (3Bh) ................................................................................................... 90

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