Tripath Technology, Inc. - Technical Information
Generating the VN12 voltage per Figure 5 is NOT recommended. Most power supplies only sink
current from the negative terminal and will not be capable of sourcing the current required by
VN12. Furthermore, problems can arise since VN12 will not track movements in VSNEG.
Setting Over-current Threshold
RS and ROCR determine the value of the over-current threshold, ISC:
ISC x RS = (VTOC x 9100)/(9100 + ROCR)
RS and ROCR are in Ω
ISC = 3 x IRMS = 3 x (POUT/RL) 0.5 (Over-current is typically set for 3 x RMS current)
VTOC = Over-current sense threshold voltage (See Electrical Characteristics Table)
= 0.75V typically
when ROCR = 0Ω, RS = (0.75)/ISC
Note that RS will dissipate approximately (IRMS)2 x RS of power. To set an ISC of 30A, for example,
with ROCR = 0Ω, means that RS = 25mΩ and RS must dissipate 2.5W on average. If ROCR = 9.1KΩ,
then to set ISC = 30A, RS will be 12.5mΩ and will only have to dissipate 1.13W on average.
As high-wattage resistors are usually only available in a few low-resistance values (10mΩ, 25mΩ
and 50mΩ), ROCR can be used to adjust for a particular over-current threshold using one of these
values for RS.
Output Transistor Selection
The key parameters to consider when selecting a MOSFET to use with the TA0103A are drain-
source breakdown voltage (BVdss), gate charge (Qg), and on-resistance (RDS(ON)).
The BVdss rating of the MOSFET needs to be selected to accommodate the voltage swing between
VSPOS and VSNEG as well as any voltage peaks caused by voltage ringing due to switching transients.
With a ‘good’ circuit board layout, a BVdss that is 50% higher than the VSPOS and VSNEG voltage
swing is a reasonable starting point. The BVdss rating should be verified by measuring the actual
voltages experienced by the MOSFET in the final circuit.
Ideally a low Qg (total gate charge) and low RDS(ON) are desired for the best amplifier performance.
Unfortunately, these are conflicting requirements since RDS(ON) is inversely proportional to Qg for a
typical MOSFET. The design trade-off is one of cost versus performance. A lower RDS(ON) means
lower I2RDS(ON) losses but the associated higher Qg translates into higher switching losses (losses =
Qg x 12 x 1.2MHz). A lower RDS(ON) also means a larger silicon die and higher cost. A higher RDS(ON)
means lower cost and lower switching losses but higher I2RDSON losses.
TA0103 – Rev 3.3/06.00