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STK10C68-5C25 View Datasheet(PDF) - Simtek Corporation

Part NameDescriptionManufacturer
STK10C68-5C25 8K x 8 nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM Simtek
Simtek Corporation Simtek
STK10C68-5C25 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
STK10C68
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK10C68-25
MIN MAX
STK10C68-35 STK10C68-45 STK10C68-55
UNITS
MIN MAX MIN MAX MIN MAX
12 tAVAV
tAVAV
tWC Write Cycle Time
25
35
45
55
ns
13 tWLWH
tWLEH
tWP Write Pulse Width
20
25
30
45
ns
14 tELWH
tELEH
tCW Chip Enable to End of Write
20
25
30
45
ns
15 tDVWH
tDVEH
tDW Data Set-up to End of Write
10
12
15
30
ns
16 tWHDX
tEHDX
tDH Data Hold after End of Write
0
0
0
0
ns
17 tAVWH
tAVEH
tAW Address Set-up to End of Write
20
25
30
45
ns
18 tAVWL
tAVEL
tAS Address Set-up to Start of Write
0
0
0
0
ns
19 tWHAX
tEHAX
tWR Address Hold after End of Write
0
0
0
0
ns
20 tWLQZh, i
tWZ Write Enable to Output Disable
10
13
14
15
ns
21 tWHQX
tOW Output Active after End of Write
5
5
5
5
ns
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be VIH during address transitions. NE VIH.
SRAM WRITE CYCLE #1: W Controlledj
ADDRESS
12
tAVAV
14
tELWH
19
tWHAX
E
18
tAVWL
W
17
tAVWH
13
tWLWH
DATA IN
DATA OUT
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
SRAM WRITE CYCLE #2: E Controlledj
ADDRESS
12
tAVAV
18
tAVEL
E
14
tELEH
16
tWHDX
21
tWHQX
19
tEHAX
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
March 2006
4 Document Control # ML0006 rev 0.2
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