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STK10C68-5C45 View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
STK10C68-5C45 8K x 8 nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM ETC1
Unspecified 
STK10C68-5C45 Datasheet PDF : 12 Pages
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STK10C68
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
STK10C68-25 STK10C68-35 STK10C68-45 STK10C68-55
UNITS
MIN MAX MIN MAX MIN MAX MIN MAX
1
tELQV
2
tAVAVf
3
tAVQVg
tACS
tRC
tAA
4
tGLQV
tOE
5
tAXQXg
tOH
6
tELQX
tLZ
7
tEHQZh
tHZ
8
tGLQX
tOLZ
9
tGHQZh
tOHZ
10
tELICCHe
tPA
11
tEHICCLd, e
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
25
35
45
55
ns
25
35
45
55
ns
25
35
45
55
ns
10
15
20
25
ns
5
5
5
5
ns
5
5
5
5
ns
10
10
12
12
ns
0
0
0
0
ns
10
10
12
12
ns
0
0
0
0
ns
25
35
45
55
ns
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note g: I/O state assumes E, G < VIL, W > VIH , and NE VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
SRAM READ CYCLE #2: E Controlledf
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
11
tEHICCL
7
tEHQZ
G
DQ (DATA OUT)
ICC
4
8
tGLQV
tGLQX
10
tELICCH
STANDBY
ACTIVE
9
tGHQZ
DATA VALID
September 2003
3 Document Control # ML0006 rev 0.1
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