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STK10C68-5C45M View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
STK10C68-5C45M 8K x 8 nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM ETC1
Unspecified 
STK10C68-5C45M Datasheet PDF : 12 Pages
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STK10C68
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a:
Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS
(VCC = 5.0V ± 10%)
SYMBOL
PARAMETER
ICC1b
Average VCC Current
ICC2c
ICC3b
ISB1d
Average VCC Current during STORE
Average VCC Current at tAVAV = 200ns
5V, 25°C, Typical
Average VCC Current
(Standby, Cycling TTL Input Levels)
ISB2d
IILK
VCC Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
IOLK
Off-State Output Leakage Current
VIH
Input Logic “1” Voltage
VIL
Input Logic “0” Voltage
VOH Note a: Output Logic “1” Voltage
VOL
Output Logic “0” Voltage
TA
Operating Temperature
COMMERCIAL
MIN
MAX
85
75
65
N/A
3
10
27
23
20
N/A
750
INDUSTRIAL/
MILITARY
MIN
MAX
90
75
65
55
3
10
28
24
21
20
1500
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
±1
±1
µA
±5
±5
µA
2.2
VCC + .5 2.2 VCC + .5
V
VSS – .5
0.8 VSS – .5 0.8
V
2.4
2.4
V
0.4
0.4
V
0
70
–40/-55 85/125
°C
NOTES
tAVAV = 25ns
tAVAV = 35ns
tAVAV = 45ns
tAVAV = 55ns
All Inputs Don’t Care, VCC = max
W (V CC – 0.2V)
All Others Cycling, CMOS Levels
tAVAV = 25ns, E VIH
tAVAV = 35ns, E VIH
tAVAV = 45ns, E VIH
tAVAV = 55ns, E VIH
E (V CC – 0.2V)
All Others VIN 0.2V or (VCC – 0.2V)
VCC = max
VIN = VSS to VCC
VCC = max
VIN = VSS to VCC, E or G VIH
All Inputs
All Inputs
IOUT = – 4mA
IOUT = 8mA
Note b:
Note c:
Note d:
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AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
480 Ohms
CAPACITANCEe (TA = 25°C, f = 1.0MHz)
SYMBOL
CIN
COUT
PARAMETER
Input Capacitance
Output Capacitance
MAX
8
7
UNITS
pF
pF
CONDITIONS
V = 0 to 3V
V = 0 to 3V
Note e: These parameters are guaranteed but not tested.
OUTPUT
255 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 1: AC Output Loading
September 2003
2 Document Control # ML0006 rev 0.1
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