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STA333BW View Datasheet(PDF) - STMicroelectronics

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STA333BW Datasheet PDF : 67 Pages
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STA333BW
Register description
Output configuration
Table 42. Output configuration
Bit R/W RST
Name
0
R/W 0
1
R/W 0
OCFG0
OCFG1
Description
Selects the output configuration
Table 43. Output configuration engine selection
OCFG[1:0]
Output configuration
2 channel (full-bridge) power, 2 channel data-out:
1A/1B 1A/1B
2A/2B 2A/2B
00
LineOut1 3A/3B
LineOut2 4A/4B
Line Out Configuration determined by LOC register
2 (half-bridge), 1(full-bridge) on-board power:
1A 1A
Binary 0 °
2A 1B
Binary 90°
01
3A/3B 2A/2B Binary 45°
1A/B 3A/B Binary 0°
2A/B 4A/B Binary 90°
2 channel (full-bridge) power, 1 channel FFX:
1A/1B 1A/1B
10
2A/2B 2A/2B
3A/3B 3A/3B
EAPDEXT and TWARNEXT Active
1 channel mono-parallel:
3A 1A/1B w/ C3BO 45°
11
3B 2A/2B w/ C3BO 45°
1A/1B 3A/3B
2A/2B 4A/4B
Config pin
0
0
0
1
Note:
To the left of the arrow is the processing channel. When using channel output mapping, any
of the three processing channel outputs can be used for any of the three inputs.
Doc ID 13773 Rev 3
33/67
 

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