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ST7571 View Datasheet(PDF) - Sitronix Technology Co., Ltd.

Part Name
Description
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ST7571
SITRONIX
Sitronix Technology Co., Ltd. SITRONIX
ST7571 Datasheet PDF : 76 Pages
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ST7571
6.4 MICROPROCESSOR INTERFACE
Microprocessor Interface Pin Description
Name
I/O
Description
RST
Reset input pin.
I
When RST is L, initialization is executed.
PS[2:0] select the microprocessor interface:
PS2 PS1 PS0
Selected Interface Mode
L
L
H Parallel 8080 MPU Interface
L
H
H Parallel 6800 MPU Interface
PS[2:0]
I
L
L
L Serial 3-Line Interface
L
H
L Serial 4-Line Interface
H
L
L Serial I2C Interface
* NOTE: It is impossible to read data from the on-chip DDRAM.
For detailed interface connection, please refer to Section 7.1 and Application Circuits.
CSB
Chip select input pin.
The interface is enabled only when CSB is "L" (except I2C Interface).
I
When CSB is non-active, DB[7:0] are high impedance.
CSB is not used in I2C interface; it is recommended to fix CSB at Hby VDD1.
Register select input pin.
A0 = H: DB0 to DB7 are display data.
A0
I
A0 = L: DB0 to DB7 are control command.
A0 is not used in serial 3-Line and I2C interface; it is recommended to fix A0 at Hby VDD1.
RWR
Write execution control pin.
PS2 PS1 PS0 MPU Type RWR
Description
Write control input pin.
I
L
H
H 6800-series R/W Keep this pin at Llevel.
The data on DB[7:0] are latched at the rising
L
L
H 8080-series /WR
edge of the /WR signal.
ERD
Read / Write execution control pin.
PS2 PS1 PS0 MPU Type ERD
Description
I
The data on DB[7:0] are latched at the falling
L H H 6800-series E
edge of the E signal.
L
L
H 8080-series /RD Keep this pin at Hlevel.
Ver 1.5a
12/76
2009/7/21
 

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