ST7260 View Datasheet(PDF) - STMicroelectronics

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ST7260

LOW SPEED USB 8-BIT MCU FAMILYWITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)

STMicroelectronics 

ST7260

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

Register or the Alternate Counter Register).

Beginning of the sequence

At t0

Read

MS Byte

LS Byte

is buffered

Other

instructions

Read

At t0 +∆t LS Byte

Returns the buffered

LS Byte value at t0

Sequence completed

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

Whatever the timer mode used (input capture, out-

put compare, One Pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

Clearing the overflow interrupt request is done in

two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of the overflow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the

mode is exited. Counting then resumes from the

previous count (MCU awakened by an interrupt) or

from the reset count (MCU awakened by a Reset).

11.2.3.2 External Clock

The external clock (where available) is selected if

CC0 = 1 and CC1 = 1 in the CR2 register.

The status of the EXEDG bit in the CR2 register

determines the type of level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

The counter is synchronized with the falling edge

of the internal CPU clock.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

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