ST7260
I/O PORTS (Cont’d)
Table 11. PA1, PA2 Description
PORT A
PA1
PA2
1Reset State
Input1
without pull-up
without pull-up
I/O
Output
Very High Current open drain
Very High Current open drain
Figure 20. PA1, PA2 Configuration
ALTERNATE ENABLE
ALTERNATE 1
OUTPUT
0
DR
LATCH
DDR
LATCH
Alternate Function
Signal
Condition
PAD
DDR SEL
DR SEL
1
0
N-BUFFER
ALTERNATE ENABLE
VSS
CMOS SCHMITT TRIGGER
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