ST7260 View Datasheet(PDF) - STMicroelectronics

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ST7260

LOW SPEED USB 8-BIT MCU FAMILYWITH UP TO 8K FLASH/ROM AND SERIAL COMMUNICATION INTERFACE (SCI)

STMicroelectronics 

ST7260

9 I/O PORTS

9.1 Introduction

The I/O ports offer different functional modes:

– Transfer of data through digital inputs and out-

puts and for specific pins

– Alternate signal input/output for the on-chip pe-

ripherals

– External interrupt generation

An I/O port consists of up to 8 pins. Each pin can

be programmed independently as a digital input

(with or without interrupt generation) or a digital

output.

9.2 Functional description

Each port is associated to 2 main registers:

– Data Register (DR)

– Data Direction Register (DDR)

Each I/O pin may be programmed using the corre-

sponding register bits in DDR register: bit X corre-

sponding to pin X of the port. The same corre-

spondence is used for the DR register.

Table 9. I/O Pin Functions

DDR

0

1

MODE

Input

Output

Input Modes

The input configuration is selected by clearing the

corresponding DDR register bit.

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

Note 1: All the inputs are triggered by a Schmitt

trigger.

Note 2: When switching from input mode to output

mode, the DR register should be written first to

output the correct value as soon as the port is con-

figured as an output.

Interrupt function

When an I/O is configured as an Input with Inter-

rupt, an event on this I/O can generate an external

Interrupt request to the CPU. The interrupt sensi-

tivity is given independently according to the de-

scription mentioned in the ITRFRE interrupt regis-

ter.

Each pin can independently generate an Interrupt

request.

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see Interrupts sec-

tion). If more than one input pin is selected simul-

taneously as an interrupt source, this is logically

ORed. For this reason if one of the interrupt pins is

tied low, the other ones are masked.

Output Mode

The pin is configured in output mode by setting the

corresponding DDR register bit (see Table 7).

In this mode, writing “0” or “1” to the DR register

applies this digital value to the I/O pin through the

latch. Therefore, the previously saved value is re-

stored when the DR register is read.

Note: The interrupt function is disabled in this

mode.

Digital Alternate Function

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over

standard I/O programming. When the signal is

coming from an on-chip peripheral, the I/O pin is

automatically configured in output mode (push-pull

or open drain according to the peripheral).

When the signal is going to an on-chip peripheral,

the I/O pin has to be configured in input mode. In

this case, the pin’s state is also digitally readable

by addressing the DR register.

Notes:

1. Input pull-up configuration can cause an unex-

pected value at the input of the alternate peripher-

al input.

2. When the on-chip peripheral uses a pin as input

and output, this pin must be configured as an input

(DDR = 0).

Warning: The alternate function must not be acti-

vated as long as the pin is configured as an input

with interrupt in order to avoid generating spurious

interrupts.

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