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ST24E64 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
ST24E64 SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM ST-Microelectronics
STMicroelectronics ST-Microelectronics
ST24E64 Datasheet PDF : 16 Pages
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ST24E64, ST25E64
Table 7. AC Characteristics
(TA = –40 to 85 °C or 0 to 70 °C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
Alt
Parameter
Min
Max
Unit
tCH1CH2
tR
Clock Rise Time
300
ns
tCL1CL2
tDH1DH2 (1)
tDL1DL1 (1)
tCHDX (2)
tF
tR
tF
tSU:STA
Clock Fall Time
SDA Rise Time
SDA Fall Time
Clock High to Input Transition
300
ns
20
300
ns
20
300
ns
600
ns
tCHCL
tHIGH
Clock Pulse Width High
600
ns
tDLCL
tHD:STA
Input Low to Clock Low (START)
600
ns
tCLDX
tHD:DAT
Clock Low to Input Transition
0
µs
tCLCH
tLOW
Clock Pulse Width Low
1.3
µs
tDXCX
tSU:DAT
Input Transition to Clock Transition
100
ns
tCHDH
tDHDL
tCLQV (3)
tCLQX
tSU:STO
tBUF
tAA
tDH
Clock High to Input High (STOP)
Input High to Input Low (Bus Free)
Clock Low to Next Data Out Valid
Data Out Hold Time
600
ns
1.3
µs
200
1000
ns
200
ns
fC
fSCL
Clock Frequency
400
kHz
tW
tWR
Write Time
10
ms
Notes: 1. Sampled only, not 100% tested.
2. For a reSTART condition, or following a write cycle.
3. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
50ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC
Figure 4. AC Testing Input Output Waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
DEVICE OPERATION (cont’d)
Memory Addressing. A data byte in the memory
is addressed through 2 bytes of address informa-
tion. The Most Significant Byte is sent first and the
Least significant Byte is sent after. The Least Sig-
nificant Byte addresses a block of 256 bytes, bits
b12,b11,b10,b9,b8 of the Most Significant Byte
select one block among 32 blocks (one block is 256
bytes).
Most Significant Byte
X X X b12 b11 b10 b9 b8
X = Don’t Care.
Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
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