ST10F280-JT3 View Datasheet(PDF) - STMicroelectronics

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Description

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ST10F280-JT3

16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM

STMicroelectronics 

ST10F280

Figure 11 : Chip Select Delay

Segment (P4)

Address (P1)

Normal Demultiplexed

Bus Cycle

ALE Lengthen Demultiplexed

Bus Cycle

ALE

Normal CSx

Unlatched CSx

BUS (P0)

RD

Data

Data

BUS (P0)

Data

Data

WR

Read/Write

Delay

Read/Write

Delay

7.2 - READY Programmable Polarity

The active level of the READY pin can be selected by software via the RDYPOL bit in the BUSCONx reg-

isters. When the READY function is enabled for a specific address window, each bus cycle within this win-

dow must be terminated with the active level defined by this RDYPOL bit in the associted BUSCON

register.

BUSCON0 (FF0Ch / 86h)

15 14 13 12 11

CSW CSRE RDY RDY -

EN0 N0 POL0 EN0

RW RW RW RW

10 9

BUS ALE

ACT0 CTL0

RW RW

SFR

8

7

6

-

BTYP

RW

5

4

MTT RWD

C0 C0

RW RW

Reset Value: 0xx0h

3

2

1

0

MCTC

RW

BUSCON1 (FF14h / 8Ah)

15 14 13 12 11

CSW CSR RDY RDY -

EN1 EN1 POL1 EN1

RW RW RW RW

10 9

BUS ALE

ACT1 CTL1

RW RW

SFR

8

7

6

-

BTYP

RW

5

4

MTT RWD

C1 C1

RW RW

Reset Value: 0000h

3

2

1

0

MCTC

RW

BUSCON2 (FF16h / 8Bh)

15 14 13 12 11

CSW CSR RDY RDY -

EN2 EN2 POL2 EN2

RW RW RW RW

10 9

BUS ALE

ACT2 CTL2

RW RW

SFR

8

7

6

-

BTYP

RW

5

4

MTT RWD

C2 C2

RW RW

Reset Value: 0000h

3

2

1

0

MCTC

RW

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