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F272-BAR-P View Datasheet(PDF) - STMicroelectronics

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Description
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F272-BAR-P Datasheet PDF : 188 Pages
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ST10F272B/ST10F272E
Pin data
Table 1. Pin description (continued)
Symbol
Pin Type
Function
118-125
128-135
P1L.0 - P1L.7
P1H.0 -
P1H.7
132
133
134
Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. PORT1 is used as the 16-bit address bus
(A) in demultiplexed bus modes: if at least BUSCONx is configured such the
demultiplexed mode is selected, the pis of PORT1 are not available for general
purpose I/O function. The input threshold of Port 1 is selectable (TTL or CMOS).
I/O Only for the ST10F272E
– The pins of P1L also serve as the additional (up to 8) analog input channels for
the A/D converter, where P1L.x equals ANy (Analog input channel y,
where y = x + 16). This additional function have higher priority on demultiplexed
bus function.
The following PORT1 pins have alternate functions:
I P1H.4 CC24IO
CAPCOM2: CC24 capture input
I P1H.5 CC25IO
CAPCOM2: CC25 capture input
I P1H.6 CC26IO
CAPCOM2: CC26 capture input
XTAL1
XTAL2
135
I P1H.7 CC27IO
CAPCOM2: CC27 capture input
138
I XTAL1 Main oscillator amplifier circuit and/or external clock input.
137
O XTAL2 Main oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in
the AC Characteristics must be observed.
XTAL3
XTAL4
RSTIN
RSTOUT
NMI
VAREF
VAGND
143
I XTAL3 32 kHz oscillator amplifier circuit input
144
O XTAL4 32 kHz oscillator amplifier circuit output
When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,
XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32
in RTCCON register shall be set. 32 kHz oscillator can only be driven by an
external crystal, and not by a different clock source.
Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for
a specified duration while the oscillator is running resets the ST10F272. An
140
I
internal pull-up resistor permits power-on reset using only a capacitor connected
to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON
register), the RSTIN line is pulled low for the duration of the internal reset
sequence.
Internal Reset Indication Output. This pin is driven to a low level during hardware,
141
O software or watchdog timer reset. RSTOUT remains low until the EINIT (end of
initialization) instruction is executed.
Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power down) instruction is executed, the NMI pin must be low in
142
I order to force the ST10F272 to go into power down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal
mode.
If not used, pin NMI should be pulled high externally.
37
- A/D converter reference voltage and analog supply
38
- A/D converter reference and analog ground
Doc ID 11917 Rev 3
21/188
 

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