ST10F272Z2Q3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

View to exact match

ST10F272Z2Q3

16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

STMicroelectronics 

Internal Flash memory

ST10F272

5.5.3 Flash non volatile access protection register 0

5.5.4

FNVAPR0 (0x08 DFB8)

NVR

Reset value: ACFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved

DBGP ACCP

RW RW

Table 20.

Bit

ACCP

DBGP

Flash non volatile access protection register 0

Function

Access Protection

This bit, if programmed at 0, disables any access (read/write) to data mapped

inside IFlash Module address space, unless the current instruction is fetched from

IFlash.

Debug Protection

This bit, if erased at 1, allows to by-pass all the protections using the Debug

features through the Test Interface. If programmed at 0, on the contrary, all the

debug features, the Test Interface and all the Flash Test Modes are disabled. Even

STMicroelectronics will not be able to access the device to run any eventual failure

analysis.

Flash non volatile access protection register 1 low

FNVAPR1L (0x08 DFBC)

NVR

Delivery value:: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDS0

RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW

Table 21.

Bit

PDS(15:0)

Flash non volatile access protection register 1 low

Function

Protections Disable 15-0

If bit PDSx is programmed at 0 and bit PENx is erased at 1, the action of bit ACCP

is disabled. Bit PDS0 can be programmed at 0 only if both bits DBGP and ACCP

have already been programmed at 0. Bit PDSx can be programmed at 0 only if bit

PENx-1 has already been programmed at 0.

38/179

Share Link: