MC14510B View Datasheet(PDF) - Motorola => Freescale
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MC14510B Datasheet PDF : 10 Pages
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PIN DESCRIPTIONS
INPUTS
P1, P2, P3, P4, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) — Active–low input used when cascading
stages. Usually connected to Carry Out of the previous
stage. While high, clock is inhibited.
Clock, (Pin 15) — BCD data is incremented or de-
cremented, depending on the direction of count, on the posi-
tive transition of this signal.
OUTPUTS
Q1, Q2, Q3, Q4, BCD outputs (Pins 6, 11, 14, 2) — BCD
data is present on these outputs with Q1 corresponding to
the least significant bit.
Carry Out, (Pin 7) — Used when cascading stages, this
pin is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
CONTROLS
PE, Preset Enable (Pin 1) — Asynchronously loads data
on the Preset Inputs. This pin is active high and will inhibit the
clock when high.
R, Reset, (Pin 9) — Asynchronously resets the Q outputs
to a low state. This pin is active high and will inhibit the clock
when high.
Up/Down, (Pin 10) — Controls the direction of count: high
for up count, low for down count.
SUPPLY PINS
VSS, Negative Supply Voltage, (Pin 8) — This pin is
usually connected to ground.
VDD, Positive Supply Voltage, (Pin 16) — This pin is con-
nected to a positive supply voltage ranging from 3.0 Vdc to
18.0 Vdc.
PRESET
ENABLE
0 = COUNT
1 = PRESET
1 = UP
0 = DOWN
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
PE
Cin
Cout
CLOCK
L.S.D.
MC14510B
U/D
R
P1
P2
P3
P4
Q5
Q6
Q7
Q8
Q1
PE
Cin
CLOCK
U/D
R
P1
Q2
Q3
M.S.D.
MC14510B
P2
P3
Q4
TERMINAL
Cout
COUNT
INDICATOR
P4
P1
P2
P3
P4
CLOCK
RESET
+ VDD
OPEN = COUNT
+ VDD
THUMBWHEEL SWITCHES
(OPEN FOR “0”)
P5
P6
P7
P8
+ VDD
RESISTORS = 10 kΩ
Note: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) does not change while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 9
(count up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one
count. The L.S.D. now counts through another cycle (10 clock pulses) and the above cycle is repeated.
Figure 3. Presettable Cascaded 8–Bit Up/Down Counter
MC14510B
356
MOTOROLA CMOS LOGIC DATA
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