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CXD1812Q/R View Datasheet(PDF) - Sony Semiconductor

Part Name
Description
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CXD1812Q/R
Sony
Sony Semiconductor Sony
CXD1812Q/R Datasheet PDF : 56 Pages
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CXD1812Q/R
3-50. INSTS1 (interrupt status 1) register (address 3DHEX)
The value of each bit in this register is that of the corresponding interrupt status. These bits are not affected by
the values of the INTEN1 register bits.
bit 7:
PFIFOFUL (packet FIFO full)
The PFIFOFUL status is established when the transfer of a 6-words (12 bytes) packet command
from the host is completed.
bit 6:
RESERVED
bit 5:
RSTCMD (reset command)
The RSTCMD status is established when an ATAPI soft reset command (08HEX) is issued from the
host.
bit 4:
STSREAD (HOST status read)
The STSREAD status is established when the ATAPI status register is read by the host after data
transfer with the host has been completed.
bit 3:
HSTCMD (host command)
The HSTCMD status is established when the command is written into the ATA command register
from the host.
bit 2:
PIONG (PIO transfer NG)
The PIONG status is established if a read/write operation is executed by the host when the IO
channel ready signal: REDY is low (not ready) during data transfer in the PIO mode.
bit 1:
XFRSTOP (transfer stop)
The XFRSTOP status is established when all transfers are completed when the automatic transfer
mode to the host is enabled.
The XFRSTOP status is also established after transfer to the host is completed by HXFRC when
the automatic transfer mode to the host is disabled.
bit 0:
BLXFRCMP (block transfer complete)
The BLXFRCMP status is established after one block transfer is completed when the automatic
transfer mode to the host is enabled.
3-51. INTEN0 (interrupt enable 0) register (address 3EHEX)
The values written to the INTEN0 register can be read as they are.
3-52. INTEN1 (interrupt enable 1) register (address 3FHEX)
The values written to the INTEN1 register can be read as they are.
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