datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

CXD1812Q/R View Datasheet(PDF) - Sony Semiconductor

Part Name
Description
View to exact match
CXD1812Q/R
Sony
Sony Semiconductor Sony
CXD1812Q/R Datasheet PDF : 56 Pages
First Prev 31 32 33 34 35 36 37 38 39 40 Next Last
CXD1812Q/R
3-49. INTSTS0 (interrupt status 0) register (address 3CHEX)
The value of each bit in this register is the value of corresponding interrupt status. These bits are not affected
by the values of the INTEN0 register bits.
bit 7:
DECINT (decoder interrupt)
This interrupt occurs when the decoder is operating a command.
(1) The DECINT status is established if the Header byte is received from CD DSP when the Sync
mark is detected or inserted while the decoder is executing the write-only, monitor-only, or real-
time correction command. However, it is not established if the Sync mark interval is less than
2352 bytes when its detection window is open.
(2) The DECINT status is established each time one correction is completed when the decoder is
in the repeat correction mode.
(3) The DECINT status is established each time 2352 bytes of data are written while the decoder
is executing the CD-DA command.
(4) The DECINT status is established when the subcode Sync mark is detected or is inserted
when the decoder is executing subcode buffering. However, it is not established if the interval
from the DECINT to the next subcode Sync mark detected is less than 98WFCK.
bit 6:
DECTOUT (decoder timeout)
The DECTOUT status is established when the Sync mark is not detected even after the time it
takes to search three sectors (40.6ms at normal speed playback) has elapsed after the decoder
has been set to the monitor-only, write-only or real-time correction mode.
bit 5:
DRVOVRN (drive overrun)
The DRVOVRN status is established when the buffering into the area assigned by DLARA is
completed while the decoder is executing the write-only, real-time correction or CD-DA command.
The DRVOVRN status is also established when the buffering into the address assigned by SLADR
is completed while the decoder is executing the subcode buffering command.
bit 4:
SUBCSYNC (subcode sync)
The SUBCSYNC status is established when the subcode Sync mark is detected or inserted while
taking-in of subcode is enabled. However, it is not established if the interval from the SUBCSYNC
to the next subcode Sync mark detected is less than 98WFCK.
If the SUBCSYNC interrupt is not cleared within 95WFCK from the interrupt, the SUBCSYNC
status is not established when the next subcode Sync mark is detected or inserted. In this case,
the subcode-Q read from the SBQDT register is not renewed.
bit 3, 2: RESERVED
bit 1:
SOFTRST (SRST detected)
The SOFTRST status is established when the host asserts the ATAPI device control register -bit 2:
SRST.
bit 0:
HARDRST (HRST detected)
The HARDRST status is established when the host asserts the HRST pin.
– 40 –
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]