CXD1812Q/R View Datasheet(PDF) - Sony Semiconductor

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CXD1812Q/R

ATAPI I/F CD-ROM DECODER

Sony Semiconductor 

CXD1812Q/R

2-51. INTEN1 (interrupt enable 1) register (address 3FHEX)

When each bit of this register is set high, the interrupt request to the sub CPU by the corresponding interrupt

status is enabled. (That is, the XINT pin becomes active in the interrupt status.) Each bit value of this register

has no effect on the corresponding interrupt status.

bit 7:

PFIFOFUL (Packet FIFO Full)

bit 6:

RESERVED

bit 5:

RSTCMD (Reset Command)

bit 4:

STSREAD (Host Status Read)

bit 3:

HSTCMD (Host Command)

bit 2:

PIONG (PIO Transfer NG)

bit 1:

XFRSTOP (Transfer Stop)

bit 0:

BLXFRCMP (Block Transfer Complete)

– 32 –

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