CXD1812Q/R View Datasheet(PDF) - Sony Semiconductor
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CXD1812Q/R Datasheet PDF : 56 Pages
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CXD1812Q/R
bit 1, 0:
WAITCYCL1, 0
These bits are valid for PIO transfer.
If the host asserts XHRD/XHWR during data transfer, the REDY pin is set low by the cycle number
set with these bits, and a wait is applied. One cycle is XTL1 cycle.
00: Wait state does not occur.
01: Wait state of 4 to 8 cycles occurs.
10: Wait state of 8 to 12 cycles occurs.
11: Wait state of 12 to 16 cycles occurs.
2-11. XFRCTL0 (transfer control 0) register (address 0AHEX)
bit 7:
AUTOXFR (auto transfer)
High: The automatic transfer mode to the host described later is enabled.
Low: The automatic transfer mode to the host above is disabled. Transfer to the host is executed
by setting HADRC and HXFRC.
bit 6 to 4: RESERVED
bit 3:
CPUDMAEN (sub CPU DMA enable)
The buffer memory access by sub CPU is enabled by setting this bit high. The sub CPU sets this
bit high after the head addresses of buffer access have been set on the CADRC.
bit 2:
CPUSRC (sub CPU source)
High: Data are transferred from sub CPU to buffer memory.
Low: Data are transferred from buffer memory to sub CPU.
bit 1 to 0: RESERVED
2-12. XFRCTL1 (transfer control 1) register (address 0BHEX)
bit 7:
PFIFOCL (packet FIFO clear)
When this bit is set high, the packet FIFO is cleared. This bit is automatically set low after FIFO
has been cleared.
bit 6:
RESERVED
bit 5:
AUTOEND (enable auto transfer termination)
The following settings are automatically made upon completion of data transfer.
High: ATAPI status register - bit 7/bit 6/bit 3: BUSY/DRDY/DRQ = Low/High/Low
ATAPI interrupt reason register - bit 1/bit 0: IO/CoD = High/High
Interrupt request signal to host: HINT = High
Low: ATAPI status register - bit 7/bit 3: BUSY/DRQ = High/Low
Interrupt request signal to host: HINT = Low
bit 4:
HSTXFREN (host transfer enable)
When this bit is set high, transfer starts between the host and buffer memory. This bit is
automatically set low when transfer is completed.
The following settings are automatically operated by setting this bit high.
ATAPI status register -bit 3: DRQ = High
ATAPI status register -bit 7: BUSY = Low (in the PIO mode)
bit 3, 2: RESERVED
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