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ACE1001LMT8 View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
MFG CO.
ACE1001LMT8 Datasheet PDF : 32 Pages
Figure 26: Crystal 9 (a) and RC (b) Oscillator Diagrams
a)
CKI
(G1)
CKO
(G0)
b)
CKI
(G1)
CKO
(G0)
1M
R
VCC
33pF
C
33pF
15.0 HALT Mode
The HALT mode is a power saving feature that almost completely
shuts down the device for current conservation. The device is
placed into HALT mode by setting the HALT enable bit (EHALT)
of the HALT register through software using only the LD M, #
instruction. EHALT is a write only bit and is automatically cleared
upon exiting HALT. When entering HALT, the internal oscillator
and all the on-chip systems including the LBD and the BOR
circuits are shut down.
The device can exit HALT mode only by the MIW circuit. There-
fore, prior to entering HALT mode, software must configure the
MIW circuit accordingly. (See Section 8.0) After a wakeup from
HALT, a 64 clock cycle start-up delay is initiated to allow the
internal oscillator to stabilize before normal execution resumes.
Immediately after exiting HALT, software must clear the Power
Mode Clear (PMC) register by only using the LD M, #instruction.
(See Figure 28)
Figure 27: HALT Register Definition
Bit 7
x
Bit 6
x
Bit 5
x
Bit 4
x
16.0 IDLE Mode
In addition to the HALT mode power saving feature, the device
also supports an IDLE mode operation. The device is placed into
IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT
register through software using only the LD M, #instruction.
EIDLE is a write only bit and is automatically cleared upon exiting
IDLE. The IDLE mode operation is similar to HALT except the
internal oscillator, the Watchdog, and the Timer 0 remain active
while the other on-chip systems including the LBD and the BOR
circuits are shut down.
The device can exit IDLE by a Timer 0 overflow every 8192 cycles
or/and by the MIW circuit. If exiting IDLE mode with the MIW, prior
to entering, software must configure the MIW circuit accordingly.
(See Section 8.0) Once a wake from IDLE mode is triggered, the
core will begin normal operation by the next clock cycle. Immedi-
ately after exiting IDLE mode, software must clear the Power
Mode Clear (PMC) register by using only the LD M, #instruction.
(See Figure 29)
Bit 3
x
Bit 2
x
Bit 1
EIDLE
Bit 0
EHALT
Figure 28: Recommended HALT Flow
Figure 29: Recommended IDLE Flow
Normal Mode
LD HALT, #01h
Multi-Input
Wakeup
Halt
LD PMC, #00h
Timer0
Overflow
Multi-Input
Wakeup
Normal Mode
LD HALT, #01H
IDLE Mode
LD PMC, #00H
Resume Normal
Mode
Resume
Normal Mode
28
ACE1001 Product Family Rev. B.1
www.fairchildsemi.com
 

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