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ACE1001M8 View Datasheet(PDF) - Fairchild Semiconductor

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ACE1001M8 Datasheet PDF : 32 Pages
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12.0 RESET block
When a RESET sequence is initiated, all I/O registers will be reset
setting all I/Os to high-impedence inputs. The system clock is
restarted after the required clock start-up delay. A reset is gener-
ated by any one of the following three conditions:
Power-on Reset (as described in Section 13.0)
Brown-out Reset (as described in Section 11.1)
Watchdog Reset (as described in Section 7.0)
13.0 Power-On-Reset
The Power-On Reset (POR) circuit is guaranteed to work if the
rate of rise of VCC is no slower than 10ms/1volt. The POR circuit
was designed to respond to fast low to high transitions between 0V
and VCC. The circuit will not work if VCC does not drop to 0V before
the next power-up sequence. In applications where 1) the VCC rise
is slower than 10ms/1 volt or 2) VCC does not drop to 0v before the
next power-up sequence the external reset option should be used.
(The external reset option is not available in the ACE1001 but is
Table 15: CMODE[0:1] Bit Definition
CMODE[0]
0
1
0
1
CMODE[1]
0
0
1
1
available in the ACE1101 and ACE1202 product families.)
14.0 CLOCK
The ACEx microcontroller has an on-board oscillator trimmed to
a frequency of 2MHz who is divided down by two yielding a 1MHz
frequency.(See AC Electrical Characteristics.) Upon power-up,
the on-chip oscillator runs continuously unless entering HALT
mode or using an external clock source. (See Figure 26.)
If required, an external oscillator circuit may be used depending on
the states of the CMODE bits of the initialization register. (See
Table 15) When the device is driven using an external clock, the
clock input to the device (G1/CKI) can range between DC to
4MHz. For external crystal configuration, the output clock (CKO)
is on the G0 pin. If an external crystal or RC is used, to yield the
corresponding instruction clock the input frequency is internally
divided down by four. If the device is configured for an external
square clock, it will not be divided.
Clock Type
Internal 1 MHz clock
External square clock
External crystal/resonator
External RC clock
Figure 25: BOR and POR Circuit Relationship Diagram (see AC Electrical Characteristics)
VCC (Pin 8)
BOR
output
VCC
1.75
0
VCC
0
VCC
Time
BOR Output
POR
output
5.0V
(Pin 7)
1.8V
0
VCC
POR
output 0
VCC
Reset
circuit
A output
Global Reset
to Logic
External
Reset
Pin
(14-Pin Only)
POR Output
Pulse
B
The Reset circuit will trigger
when inputs A or B transition
from High to Low. At that time
the Global Reset signal will go
high which will reset all controller
logic. The Global Reset will go
high and stay high for around 1µs.
27
ACE1001 Product Family Rev. B.1
www.fairchildsemi.com
 

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