ACE1001LM8X View Datasheet(PDF) - Fairchild Semiconductor

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ACE1001LM8X

Arithmetic Controller Engine (ACEx™) for Low Power Applications

Fairchild Semiconductor 

Negative (N)

The negative flag is set if the MSB of the result from an arithmetic,

logic, or data manipulation operation is set to one. Otherwise, the

flag is cleared. A result is said to be negative if its MSB is a one.

Interrupt Mask (G)

The interrupt request mask (G) is a global mask that disables all

maskable interrupt sources. If the G Bit is cleared, interrupts can

become pending, but the operation of the core continues uninter-

rupted. However, if the G Bit is set an interrupt is recognized. After

any reset, the G bit is cleared by default and can only be set by a

software instruction. When an interrupt is recognized, the G bit is

cleared after the PC is stacked and the interrupt vector is fetched.

Once the interrupt is serviced, a return from interrupt instruction is

normally executed to restore the PC to the value that was present

before the interrupt occurred. The G bit is the reset to one after a

return from interrupt is executed. Although the G bit can be set

within an interrupt service routine, “nesting” interrupts in this way

should only be done when there is a clear understanding of latency

and of the arbitration mechanism.

4.2 Interrupt handling

When an interrupt is recognized, the current instruction completes

its execution. The return address (the current value in the program

counter) is pushed onto the stack and execution continues at the

address specified by the unique interrupt vector (see Table 11).

This process takes five instruction cycles. At the end of the

interrupt service routine, a return from interrupt (RETI) instruction

is executed. The RETI instruction causes the saved address to be

pulled off the stack in reverse order. The G bit is set and instruction

execution resumes at the return address.

The ACEx microcontroller is capable of supporting four interrupts.

Three are maskable through the G bit of the SR and the fourth

(software interrupt) is not inhibited by the G bit (see Figure 12). The

software interrupt is generated by the execution of the INTR

instruction. Once the INTR instruction is executed, the ACEx core

will interrupt whether the G bit is set or not. The INTR interrupt is

executed in the same manner as the other maskable interrupts

where the program counter register is stacked and the G bit is

cleared. This means, if the G bit was enabled prior to the software

interrupt the RETI instruction must be used to return from interrupt

in order to restore the G bit to its previous state. However, if the

G bit was not enabled prior to the software interrupt the RET

instruction must be used.

In case of multiple interrupts occurring at the same time, the ACEx

microcontroller core has prioritized the interrupts. The interrupt

priority sequence in shown in Table 8.

4.3 Addressing Modes

The ACEx microcontroller has six addressing modes indexed,

direct, immediate, absolute jump, and relative jump.

Indexed

The instruction allows an 8-bit unsigned offset value to be added

to the 10-LSBs of the X-pointer yielding a new effective address.

This mode can be used to address any memory space (program

or data).

Direct

The instruction contains an 8-bit address field that directly points

to the data memory space as an operand.

Immediate

The instruction contains an 8-bit immediate field as an operand.

Inherent

This instruction has no operands associated with it.

Absolute

The instruction contains a 10-bit address that directly points to a

location in the program memory space. There are two operands

associated with this addressing mode. Each operand contains a

byte of an address. This mode is used only for the long jump (JMP)

and JSR instructions.

Relative

This mode is used for the short jump (JP) instructions where the

operand is a value relative to the current PC address. With this

instruction, software is limited to the number of bytes it can jump,

-31 or +32.

Table 8: Interrupt Priority Sequence

Priority (4 highest, 1 lowest)

4

3

2

1

Interrupt

MIW (EDGEI)

Timer0 (TMRI0)

Timer1 (TMRI1)

Software (INTR)

14

ACE1001 Product Family Rev. B.1

www.fairchildsemi.com

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