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AD9873 View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD9873 Datasheet PDF : 39 Pages
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AD9873
AGND
AGND IQ
AVDD 1
80 AGND IQ
DRGND 2
0.1F
0.1F
0.1F
10F
0.1F
79 I IN+
DRVDD 3
(MSB) IF(11) 4
0.1F
IF(10) 5
AD9873
78 I IN
77 AGND IQ
76 REFT8
IF(9) 6
IF(8) 7
IF(7) 8
MQFP
TOP VIEW
(Pins Down)
10F
0.1F
75 REFB8
74 AGND IQ
73 AVDD IQ
IF(6) 9
72 DRVDD
IF(5) 10
10F
0.1F
71 REF CLK
IF(4) 11
70 DRGND
IF(3) 12
69 DGND SD
IF(2) 13
IF(1) 14
10F
0.1F
68 SDELTA0
67 SDELTA1
IF(0) 15
(MSB) Rx IQ(3) 16
66 DVDD SD
65 CA_ENABLE
VAS
Rx IQ(2) 17
64 CA DATA
Rx IQ(1) 18
Rx IQ(0) 19
Rx SYNC 20
EXTERNAL
0.1F
POWER SUPPLY
DECOUPLING
63 CA CLK
62 DVDD OSC
61 OSCIN OSC GND
DRGND 21 0.1F
VDR
DRVDD 22
MLCK 23
VDS
DVDD 24
10F
0.1F 0.01F
60 XTAL
59 DGND OSC
58 AGND PLL
57 PLL FILTER
DGND 25
56 AVDD PLL
Tx SYNC 26
(MSB) Tx IQ(5) 27
Tx IQ(4) 28
Tx IQ(3) 29
0.1F
10F
0.1F
0.1F
10F
0.01F
0.1F 0.1F 0.01F
55 DVDD PLL
54 DGND PLL
53 AVDD Tx
52 Tx+
Tx IQ(2) 30
0.01F
51 Tx
DGND
Tx GND
Figure 24. Power Supply Decoupling
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed and high
performance, the implementation and construction of the printed
circuit board design is often as important as the circuit design.
Proper RF techniques must be used in device selection, placement,
routing, supply bypassing, and grounding. Figure 24 illustrates
proper power supply decoupling. Split-ground technique can
be used to isolate digital and high-speed clock generation noise
from the analog front ends. The analog front end may be
further split to minimize crosstalk between the transmit and
receive sections. Noise-sensitive video-IF signals can also be
separated from the more robust IQ-ADC signal path. One com-
mon ground underneath the chip connects all ground splits and
assures short distances for ground pin connections. Figure 24
uses two separate power supplies. VAS powers the analog and
clock generation section of the chip while VDS is used for the
digital signals of the chip. An extra power supply VDR is only
needed in applications that require lower level digital outputs.
DRVDD and DVDD pins should be connected together for normal
mode. VDS (and VDR) should not be directly connected to the
power supply of noisy digital signal processing chips. It might
even be considered as an analog supply. Ferrite beads and 10 F
decoupling capacitors isolate power supplies between functional
blocks. Each supply pin is further decoupled with a 0.1 F multi-
layer ceramic capacitor that is mounted as close as possible to
the pin. In the high-speed PLL and DAC sections additional
0.01 F capacitors may be required as shown in Figure 24.
–32–
REV. 0
 

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