datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

SN74LS253D View Datasheet(PDF) - ON Semiconductor

Part Name
Description
View to exact match
SN74LS253D Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
SN74LS253
LOGIC DIAGRAM
E0b
I3b
I2b
I1b
I0b
S0
S1
15
13
12
11
10
14
2
I3a
3
I2a
I1a
4
5
I0a
6
E0a
1
Zb 9
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
Za 7
FUNCTIONAL DESCRIPTION
The LS253 contains two identical 4-Input Multiplexers
with 3-state outputs. They select two bits from four sources
selected by common select inputs (S0, S1). The 4-input
multiplexers have individual Output Enable (E0a, E0b)
inputs which when HIGH, forces the outputs to a high
impedance (high Z) state.
The LS253 is the logic implementation of a 2-pole,
4-position switch, where the position of the switch is
determined by the logic levels supplied to the two select
inputs. The logic equations for the outputs are shown below:
Za = E0a (I0a S1 S0 + I1a S1 S0 I2a S1 S0 + I3a S1 S0)
Zb = E0b(I0b S1 S0 + I1bS1S0 I2bS1S0 + I3bS1S0)
If the outputs of 3-state devices are tied together, all but
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
TRUTH TABLE
SELECT
INPUTS
DATA INPUTS
OUTPUT
ENABLE
S0
S1
I0
I1
I2
I3
E0
X
X
X
X
X
X
H
L
L
L
X
X
X
L
L
L
H
X
X
X
L
H
L
X
L
X
X
L
H
L
X
H
X
X
L
L
H
X
X
L
X
L
L
H
X
X
H
X
L
H
H
X
X
X
L
L
H
H
X
X
X
H
L
H = HIGH Level
L = LOW Level
X = Irrelevant
(Z) = High Impedance (off)
Address inputs S0 and S1 are common to both sections.
OUTPUT
Z
(Z)
L
H
L
H
L
H
L
H
http://onsemi.com
3
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]