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SN54LS109A View Datasheet(PDF) - Motorola => Freescale

Part Name
Description
View to exact match
SN54LS109A
Motorola
Motorola => Freescale Motorola
SN54LS109A Datasheet PDF : 4 Pages
1 2 3 4
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS109A consists of two high speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise
and fall times of the clock waveform. The JK design allows operation as a D
flip-flop by simply connecting the J and K pins together.
LOGIC DIAGRAM
SET (SD)
5(11)
CLEAR (CD)
1(15)
CLOCK
4(12)
J
2(14)
K
3(13)
Q
6(10)
Q
7(9)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
SD CD J
OUTPUTS
KQQ
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
LHXXHL
HLXXLH
L L XXHH
HHh hHL
HH
l
hq
q
HH h
l
q
q
HH l
l
LH
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the LOW to HIGH clock transition.
SN54/74LS109A
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
5
11
2
J SD Q
6 14 J SD Q
10
4
CP
12
CP
7 13
3
K CD Q
K CD Q
9
1
15
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-181
 

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