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74ALVCH162268ZQLR View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
74ALVCH162268ZQLR 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS TI
Texas Instruments TI
74ALVCH162268ZQLR Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
www.ti.com
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
FEATURES
Member of the Texas Instruments Widebus™
Family
DGG OR DL PACKAGE
(TOP VIEW)
Operates From 1.65 V to 3.6 V
Max tpd of 4.8 ns at 3.3 V
• ±24-mA Output Drive at 3.3 V
B-Port Outputs Have Equivalent 26-Series
Resistors, So No External Resistors Are
Required
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
OEA 1
CLKEN1B 2
2B3 3
GND 4
2B2 5
2B1 6
VCC 7
A1 8
A2 9
A3 10
GND 11
56 OEB
55 CLKENA2
54 2B4
53 GND
52 2B5
51 2B6
50 VCC
49 2B7
48 2B8
47 2B9
46 GND
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
A4 12
A5 13
A6 14
A7 15
45 2B10
44 2B11
43 2B12
42 1B12
DESCRIPTION/ORDERING INFORMATION
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V VCC operation.
A8 16
A9 17
GND 18
A10 19
41 1B11
40 1B10
39 GND
38 1B9
The SN74ALVCH162268 is used for applications in
which data must be transferred from a narrow
high-speed bus to a wide, lower-frequency bus.
The device provides synchronous data exchange
between the two ports. Data is stored in the internal
registers on the low-to-high transition of the clock
(CLK) input when the appropriate clock-enable
(CLKEN) inputs are low. The select (SEL) line is
synchronous with CLK and selects 1B or 2B input
data for the A outputs.
A11 20
A12 21
VCC 22
1B1 23
1B2 24
GND 25
1B3 26
CLKEN2B 27
SEL 28
37 1B8
36 1B7
35 VCC
34 1B6
33 1B5
32 GND
31 1B4
30 CLKENA1
29 CLK
For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single
storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be
presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables
(OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-resistors to reduce overshoot
and undershoot.
TA
-40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
SSOP - DL
Tube
Tape and reel
SN74ALVCH162268DL
SN74ALVCH162268DLR
TSSOP - DGG
Tape and reel
SN74ALVCH162268GR
VFBGA - GQL
VFBGA - ZQL (Pb-free)
Tape and reel
SN74ALVCH162268KR
74ALVCH162268ZQLR
TOP-SIDE MARKING
ALVCH162268
ALVCH162268
VH2268
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2004, Texas Instruments Incorporated
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