HD6437049 View Datasheet(PDF) - Renesas Electronics

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HD6437049

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7000 Series

Renesas Electronics 

Figure 12.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 358

Figure 12.9 Sample Serial Reception Data Flowchart (1) .......................................................... 360

Figure 12.9 Sample Serial Reception Data Flowchart (2) .......................................................... 361

Figure 12.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A) .......................................... 363

Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 364

Figure 12.12 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 365

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 366

Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 367

Figure 12.14 Data Format in Clocked Synchronous Communication (For LSB-First) .............. 368

Figure 12.15 Sample SCI Initialization Flowchart ..................................................................... 369

Figure 12.16 Sample SCI Transmission Operation in Clocked Synchronous Mode .................. 370

Figure 12.17 Sample Serial Transmission Flowchart ................................................................. 371

Figure 12.18 Example of SCI Operation in Reception ............................................................... 372

Figure 12.19 Sample Serial Reception Flowchart ...................................................................... 373

Figure 12.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ...... 375

Figure 12.21 Example of Clocked Synchronous Transmission with DTC ................................. 378

Section 13 A/D Converter

Figure 13.1 Block Diagram of A/D Converter (For One Module) ............................................. 380

Figure 13.2 A/D Conversion Timing.......................................................................................... 389

Figure 13.3 External Trigger Input Timing ................................................................................ 390

Figure 13.4 Definitions of A/D Conversion Accuracy ............................................................... 393

Figure 13.5 Definitions of A/D Conversion Accuracy ............................................................... 393

Figure 13.6 Example of Analog Input Circuit ............................................................................ 394

Figure 13.7 Example of Analog Input Protection Circuit........................................................... 396

Figure 13.8 Analog Input Pin Equivalent Circuit ....................................................................... 396

Section 14 Compare Match Timer (CMT)

Figure 14.1 CMT Block Diagram............................................................................................... 397

Figure 14.2 Counter Operation ................................................................................................... 400

Figure 14.3 Count Timing .......................................................................................................... 401

Figure 14.4 CMF Set Timing...................................................................................................... 402

Figure 14.5 Timing of CMF Clear by the CPU .......................................................................... 402

Figure 14.6 CMCNT Write and Compare Match Contention .................................................... 403

Figure 14.7 CMCNT Word Write and Increment Contention .................................................... 404

Figure 14.8 CMCNT Byte Write and Increment Contention...................................................... 405

Section 15 Controller Area Network 2 (HCAN2)

Figure 15.1 HCAN2 Block Diagram .......................................................................................... 408

Figure 15.2 Register Configuration ............................................................................................ 412

Figure 15.3 Standard Format ...................................................................................................... 447

Rev. 2.00, 09/04, page xxx of xl

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