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SAK-XC2765X-104FXXL View Datasheet(PDF) - Infineon Technologies

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Description
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SAK-XC2765X-104FXXL
Infineon
Infineon Technologies Infineon
SAK-XC2765X-104FXXL Datasheet PDF : 123 Pages
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XC2765X
XC2000 Family Derivatives / Base Line
General Device Information
Table 5
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
2,
VDDPB
25,
27,
50,
52,
75,
77,
100
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent VDDP/
VSS pin pairs as close as possible to the pins.
Note: The on-chip voltage regulators and all ports
except P5, P6 and P15 are fed from supply
voltage VDDPB.
1, VSS
26,
51,
76
-
PS/-- Digital Ground
All VSS pins must be connected to the ground-line
or ground-plane.
Note: Also the exposed pad is connected
internally to VSS. To improve the EMC
behavior, it is recommended to connect the
exposed pad to the board ground.
For thermal aspects, please refer to
Section 5.1. Board layout examples are
given in an application note.
1) To generate the reference clock output for bus timing measurement, fSYS must be selected as source for
EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This
configuration is referred to as reference clock output signal CLKOUT.
Data Sheet
34
V2.0, 2009-03
 

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