SAF7115 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

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SAF7115

Multistandard video decoder with super-adaptive comb filter, scaler and VBI data read-back via I2C-bus

NXP Semiconductors. 

NXP Semiconductors

SAF7115

Multistandard video decoder

Table 4.

Symbol

XRDY

Pin description …continued

Pin

HTQFP100 TFBGA160

96

A4

Type[1]

O

XRH

92

A6

I/O

XRV

91

B6

I/O

XTRI

80

A12

I/pd

Host port (H-port)

HPD7

64

G13

I/O

HPD6

65

G14

I/O

HPD5

66

F13

I/O

HPD4

67

F14

I/O

HPD3

69

E14

I/O

HPD2

70

D13

I/O

HPD1

71

D14

I/O

HPD0

72

C13

I/O

Description

task flag or read signal from scaler, controlled by bit XRQT

(subaddress 83h)

horizontal reference I/O expansion-port: in 10-bit video output

mode: this signal represents the video bit 1

vertical reference I/O expansion-port: in 10-bit video output mode:

this signal represents the video bit 0 (LSB)

X-port output control signal, affects all X-port pins (XPD[7:0],

XRH, XRV, XDQ and XCLK) enable and active polarity is under

software control (bits XPE in subaddress 83h)

MSB of host port data I/O, carries CbCr chrominance information

in 16-bit video I/O modes

MSB − 1 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

MSB − 2 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

MSB − 3 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

MSB − 4 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

MSB − 5 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

MSB − 6 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

LSB of host port data I/O, carries CbCr chrominance information

in 16-bit video I/O modes

[1] A = analog, I = input, O = output, P = power, st = strapping, pu = pull-up, pd = pull-down, od = open-drain.

[2] For CGC1 and CGC2.

[3] For analog inputs AI1x.

[4] For analog inputs AI2x.

[5] For normal operation connect pins AI1D and AI2D to ground through a capacitor. In principle both analog input stages can operate in

differential mode, too, depending on the application. This may be interesting for differential video (CVBS). Please contact NXP for more

information.

[6] This contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier phase and

frequency and PAL sequence (according to RTC level 3.1, refer to external document RTC Functional Specification for details), can be

strapped to supply through a 3.3 kΩ resistor to change the default I2C-bus read and write addresses from 42h and 43h (internal

pull-down) to 40h and 41h.

[7] According to the IEEE1149.b1-1994 standard pins TDI and TMS are input pins with an internal pull-up transistor and TDO is a 3-state

output pin. Pins TCK and TRST_N are also built with internal pull-up.

[8] This pin provides easy initialization of BST circuitry. Pin TRST_N can be used to force the Test Access Port (TAP) controller to the

test-logic-reset state (normal operation) at once.

SAF7115_1

Product data sheet

Rev. 01 — 15 October 2008

© NXP B.V. 2008. All rights reserved.

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